System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Abstract

Abstract-Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottleneck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-theart industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.

Power-aware multi-core simulation for early design stage hardware/software co-optimization

“…Using Micron's DDR3 System-Power calculator [21], we calculate idle (static plus refresh) power and per-operation energy for reads and writes. Power consumption of the DRAM interface, both for the regular DDR3 case as for 3D stacked memory, is calculated according to the models from [9]. We thus calculate static and dynamic DRAM chip and interface power, and add these to McPAT's power numbers.…”

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

“…In 3D stacked ICs, TSV interconnects enable low-parasitic direct connections between tiers and can allow for considerable energy savings when compared to traditional PCB chip-to-chip interconnections [2]. However, TSV parasitic capacitance can still become an important source of energy dissipation in large, densely interconnected 3D SoCs, since the combined capacitance and thus the energy required to drive TSVs, will increase linearly with the number of tiers and interconnections.…”

DRAM selection and configuration for real-time mobile systems

“…The footprint for a single channel is calculated by A footprint = Area/8, because all 3D-DRAM cubes are composed of 8 layers. In contrast to [8], we use a TSV diameter value of 8 μm and 16 μm pitch. This diameter and pitch are a good compromise between reported yield and density.…”

“…First, reducing the need of IO drivers and interconnect compared to off-chip memories results in significant power savings [7]. Second, the excellent electrical characteristics of Through Silicon Via (TSV) enable the use of low-power CMOS transceivers, which save up to 98% of interface power [8]. Third, the low area requirement of TSVs makes it possible to have much wider memory interfaces that enable significantly higher bandwidth [9].…”