Switched-Capacitor Techniques For High-Accuracy Filter And ADC Design

Quinn, Patrick; Roermund, Arthur van

doi:10.1007/978-1-4020-6258-2

Cited by 21 publications

(21 citation statements)

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“…consuming 30-40 % of the total power consumption) [6,7,10,11]. The power consumption of succeeding stages is decreased strongly by stage scaling [6,7,10]. Therefore, the parallel-sampling architecture is only applied to the first stage of a 12-b switched-capacitor pipeline ADC for the purpose of improving the ADC power efficiency for multi-carrier signals.…”

Section: A Parallel-sampling First Stage For a Pipeline Adcmentioning

confidence: 99%

“…The first stage of a pipeline ADC is the most critical one in terms of speed and noise performance, hence dominating the power consumption of the ADC (e.g. consuming 30-40 % of the total power consumption) [6,7,10,11]. The power consumption of succeeding stages is decreased strongly by stage scaling [6,7,10].…”

Section: A Parallel-sampling First Stage For a Pipeline Adcmentioning

confidence: 99%

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Implementations of the Parallel-Sampling ADC Architecture

Lin

Hegt

Doris

et al. 2015

Analog Circuits and Signal Processing

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This chapter describes circuit implementations of the parallel-sampling ADC architecture presented in Chap. 3. The parallel-sampling architecture is applied to two ADC architectures (a pipeline and a time-interleaving SAR ADC architecture), which are suitable for designing high-speed and medium-to-high resolution ADCs, to improve the ADC power efficiency for multi-carrier signals. Section 4.1 describes the architecture and operation of a 200 MS/s 12-b switchedcapacitor pipeline ADC with a parallel-sampling first stage, which is suitable for broadband multi-carrier receivers for wireless standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac) . A circuit implementation of the parallel-sampling first stage of the pipeline ADC is presented and simulation results are given. Section 4.2 presents the architecture and operation of a 4 GS/s 11 b timeinterleaved ADC with a parallel-sampling frontend stage, which targets wideband direct sampling receivers for DOCSIS 3.0 cable modems . Circuit implementation and simulation of the 4 GS/s parallel-sampling frontend stage are given. Due to the complexity of implementing the proposed 4 GS/s ADC on chip, a two-step design approach was adopted. In Sect. 4.3, a prototype IC of an 11 b 1 GS/s ADC with a parallel sampling architecture is presented, which serves as a first step to validate the parallel-sampling ADC concept and the performance of the high-speed parallelsampling frontend and detection circuits. In future work, the frontend stage of the IC can be interleaved by four times to achieve the aggregate sample rate of 4 GHz of the proposed ADC discussed in Sect. 4.2. Conclusions of this chapter are drawn in Sect. 4.4.

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Section: A Parallel-sampling First Stage For a Pipeline Adcmentioning

confidence: 99%

Section: A Parallel-sampling First Stage For a Pipeline Adcmentioning

confidence: 99%

Implementations of the Parallel-Sampling ADC Architecture

Lin

Hegt

Doris

et al. 2015

Analog Circuits and Signal Processing

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“…Now the system is operating at discrete points of time, so that we talk about discrete-time modulators. They are typically realized with the switched-capacitor technique, which is presented in this chapter [19]. The idea is illustrated in Fig.…”

Section: Switched-capacitor Approachmentioning

confidence: 99%

Basics on Delta-Sigma Converters

Ohnhäuser¹

2015

Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters

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Industrial applications often require a high resolution and performance from an analog-to-digital converter at a moderate speed (see Chap. 1), so that SAR ADCs (Chaps. 2 and 3) and delta-sigma ADCs are most commonly used. This chapter will therefore concentrate on the basics of delta-sigma converters and then on the discrete-time approach utilizing the switched-capacitor technique, which is most commonly used. The alternative continuous-time architecture will be discussed in Chap. 5.Delta-sigma converters were already introduced in Chap. 1. The analog signal A is coupled to a filter with feedback-loop as illustrated again in Fig. 4.1.The quantizer, which in Fig. 4.1 is a comparator, is placed within a regulationloop, resulting in the transfer function of Eq. (1.21):The quantization noise N is suppressed within the low frequency signal band and the remaining high frequency noise is suppressed by a digital low-pass filter. This way, the delta-sigma converters achieve the best signal-to-noise ratios [1]. ΔΣ ADCs can convert signals with low signal frequency with high resolution. The oversampling and the digital low-pass filtering will even suppress higher frequency noise of the signal. Such signals occur often in industrial applications that use sensors. Examples are pressure or temperature sensors, flow or energy meters. Additionally, the analog filter provides a linear transfer function. Consequently, the differential non-linearity is extremely good. However, non-linear parameters of the electrical circuitry will still cause an integral non-linearity.Further disadvantages are the low conversion rates caused by the required oversampling, the time delay caused by the digital filter and the fact that snapshots are not possible as the delta-sigma converter has to run continuously and synchronously with the clock.

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“…For this measurement, only the reference current cell waveform is integrated (see (1), with I DAC = 0). When first applying the timing calibration of the polarity waveform and then the normal current cell calibration, the resulting calibration error is given in (7).…”

Section: Polarity Waveform Calibrationmentioning

confidence: 99%

“…This relationship is analyzed in [7], and leads to the following capacitor sizes: C f b =700fF and the other capacitors are 170fF.…”

Section: A Switched Capacitor Circuitmentioning

confidence: 99%

Timing error measurement for highly linear wideband Digital to Analog Converters

Bechthum

Tang

Hegt

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical.A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.

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Switched-Capacitor Techniques For High-Accuracy Filter And ADC Design

Cited by 21 publications

References 0 publications

Implementations of the Parallel-Sampling ADC Architecture

Implementations of the Parallel-Sampling ADC Architecture

Basics on Delta-Sigma Converters

Timing error measurement for highly linear wideband Digital to Analog Converters

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