Timing error measurement for highly linear wideband Digital to Analog Converters

Analog Integr Circ Sig Process

Briaire³

et al. 2015

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This paper proposes a classification of Mixing-DAC architectures, focusing on spectral purity. Based on literature research, analysis and simulations, the proposed classification shows the impact of architectural choices on the output spectral purity. To concretize the classification and validate the analysis, a number of specific Mixing-DAC architectures are synthesized, discussed and simulated. Given the proposed classification, a set of optimal architectural choices lead to a strong architecture candidate for achieving high spectral purity at high signal frequencies, i.e. SFDR [ 80 dBc at f OUT = 4 GHz for current and future multicarrier GSM applications. The main characteristics of this architecture are: Cartesian signaling, local Gilbert-cell mixing and a fully differential implementation.

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Section: Smart Methodsmentioning

confidence: 99%

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Analog Integr Circ Sig Process

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et al. 2015

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“…Numerous timing error calibration techniques for CS DACs exist [5]- [7] but they are not considered since it is assumed that they are equally applicable to all proposed architectures.…”

Section: A Architecture Optionsmentioning

confidence: 99%

A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

Briaire³

et al. 2014

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General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SF DRRBW =85dBc), the delay spread σ(delay) should be <36fs. Therefore, only mixing in the output stage with a single LO driver can achieve the desired linearity.The presented analysis shows that the timing of the binary cells in the segmented converter is very important, especially in a back-off scenario. Simulations confirm that accurate capacitance scaling at the high-frequency nodes of the binary current cells is crucial. A new, back-off aware segmentation trade-off is proposed, which shows the impact of the SF DRRBW and backoff requirements on the segmentation choice.The proposed methods result in an optimal Mixing-DAC architecture, implemented in 65nm CMOS, with a simulated performance of SF DRRBW =86dBc at 4GHz output frequency and -16dB FS /tone output power (10dB back-off).

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Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM

2012 IEEE International Symposium on Circuits and Systems

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et al. 2012

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