Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Kumar, Prashant; Vashisht, Munish; Gupta, Neeraj; Gupta, Rashmi

doi:10.1007/s12633-021-01399-4

Cited by 10 publications

(6 citation statements)

References 34 publications

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“…SS depends on the first term only and has a value of 60 mV/decade [22]. The effect of high-k materials on the sub-threshold slope of the 32nm DG-JLFETs is shown in Figure 6.…”

Section: Sub-threshold Slopementioning

confidence: 99%

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Kumar

Vashishath

Gupta

et al. 2022

Silicon

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This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson's equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

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“…SS depends on the first term only and has a value of 60 mV/decade [22]. The effect of high-k materials on the sub-threshold slope of the 32nm DG-JLFETs is shown in Figure 6.…”

Section: Sub-threshold Slopementioning

confidence: 99%

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Kumar

Vashishath

Gupta

et al. 2022

Silicon

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“…The curves begin to decline owing to the charge carriers' saturation mobility, which is what causes parasitic capacitances to exist. (10) Higher the GTFP value, better is the device performance. So, from the Fig.…”

Section: Fig 9 Tgf As a Function Of Vgsmentioning

confidence: 99%

“…Various analytical study of surface potential for junctionless transistor has also been done [6], [7]. It has also been reported that cylindrical surrounding gate MOSFETs shows good switching performance and also can be used for microwave frequency applications [8], [9], [10]. However, the junctionless transistor poses various limitations such as degraded mobilities due to high doping concentrations.…”

Section: Introductionmentioning

confidence: 99%

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Yadav

Rewari

Pandey

2022

Silicon

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In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

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“…It provides higher voltage gain; hence SOI MOSFET device with high-k dielectric can be used for amplification purpose. Thus, it is better option for upcoming SOI MOSFET devices [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Fully Depleted SOI (FD-SOI) MOSFET Incorporating Dielectric Engineering

Kumar

Vashishath

Gupta

et al. 2022

IOP Conf. Ser.: Mater. Sci. Eng.

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This paper presents an efficacy of an FD SOI MOSFET structure in suppressing short channel effects is investigated through 2-Dimenional simulation on ATLAS Silvaco. The electrical comparison between Bulk MOSFET, FD-SOI MOSFET and FD-SOI MOSFET using high-k gate dielectric at 45nm technology has been carried out. The structures have been designed and study of threshold voltage, sub threshold slope, drain current (Ion), leakage current (Ioff), Ion/Ioff, transconductance has been done. The features offered by the new device structure are found to be better than the conventional bulk MOSFET. Aluminum Oxide (Al2O3) has been compared to SiO2 as dielectric material. As the dielectric constant of the materials increased, there is a reduction in the leakage current. It provides higher transconductance and better subthreshold slope, thus resulting in improvement of the device. A comparative analysis has been carried out among bulk MOSFET and SOI MOSFET using aluminum oxide, silicon oxide and silicon nitride as gate dielectric materials. Aluminum Oxide also provides higher drain current as compared to other dielectric materials presented in the paper. Thus, Aluminum Oxide is a good candidate as a dielectric for the future devices as compared to traditional oxides. The proposed device can be useful for low power applications.

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Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Cited by 10 publications

References 34 publications

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Performance Analysis of Fully Depleted SOI (FD-SOI) MOSFET Incorporating Dielectric Engineering

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