Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Abstract

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

“…Due to this conduction, the varying depletion capacitance effectively matches ferroelectric and internal capacitance, reducing the hysteresis. Thus, this JAM‐based ferroelectric structure solves the major issue of hysteresis in such FE‐FETs 8,36 …”

“…Thus, this JAM-based ferroelectric structure solves the major issue of hysteresis in such FE-FETs. 8,36 4 | MODEL…”

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

“…In traditional DG MOSFETs, independent gate operation is utilized to enhance performance of devices, diminish V th -roll-off, and improve DIBL to suppress SCEs. Furthermore, the independent gate operation is also leveraged in JL-MOSFET structures to enhance manufacturing process and enable logical operations without need for traditional junctions [18,19]. Additionally, DG MOSFETs with gate underlap structures is utilized to regulate SCEs with enhancing performance of device for low-power applications [20][21][22][23].…”