Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

Burignat, Stéphane; Flandre, Denis; Arshad, Mohd Khairuddin; Kilchytska, Valeriya; Andrieu, F.; Faynot, O.; Raskin, Jean‐Pierre

doi:10.1016/j.sse.2009.12.021

Cited by 45 publications

(25 citation statements)

References 33 publications

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“…which are in qualitative agreement with the simulation results of the mean channel position in UTBB FD-SOI MOSFETs [25]. The model values of V tf were obtained using φ f = 0.37 V, A c = 0.2, and B c = 3.1 V for the devices of the investigated SOI technology.…”

Section: Discussion On the Threshold Voltage Modelsupporting

confidence: 84%

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Karatsori

Tsormpatzoglou

Theodorou

et al. 2015

IEEE Trans. Electron Devices

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An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from −3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools. Index Terms-Back-gate control, compact model, fully depleted silicon-on-insulator (FD-SOI) ultrathin-body and box (UTBB) MOSFETs. 0018-9383

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Section: Discussion On the Threshold Voltage Modelsupporting

confidence: 84%

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Karatsori

Tsormpatzoglou

Theodorou

et al. 2015

IEEE Trans. Electron Devices

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“…The quantum confinement generates no current conduction at the front interface, but at a distance x c from the front interface (9,10). For this reason, the value of x c can be calculated using equation [8], where A C and B C are model parameters:…”

Section: Device Characteristicsmentioning

confidence: 99%

“…Due to this effect the effective value of the silicon film thickness (t Si ) and front oxide thickness (t oxf ) are determined by the equations [9] and [10]: Applying the model in Dynamic Threshold mode By the V T x V GB curve calculated from the analytical model, it is possible to determine the value of V T of the UTBB operating in: DT, eDT and inverse-eDT modes.…”

Section: Device Characteristicsmentioning

confidence: 99%

Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

et al. 2015

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This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) devices with Ground Plane (GP) implantation operating in three dynamic modes, simple Dynamic Threshold (DT), enhanced DT and inverse eDT mode. The analytical model is based on the Martino et al model adding the quantum confinement effect. The results show that the analytical model proposed has a good agreement to experimental data.

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“…The SCEs, which mainly includes the threshold voltage roll-off, the drain induced barrier lowering (DIBL), and the subthreshold swing degradation, is the major barrier for MOSFET downscaling. Therefore, based on the UTBB SOI technology, a number of methods have been proposed to further reduce the SCEs, by employing the channel engineering, the source/drain engineering (Yamada et al 2013b, c;Srivastava et al 2016), the back-biasing technique (Burignat et al 2010;Karatsori et al 2015), the thickness modulation of the buried oxide layer (Yamada et al 2013a), and the gate voltage difference engineering (Anvarifard et al 2009;Anvarifard and Orouji 2013;Lahgere et al 2015).…”

Section: Introductionmentioning

confidence: 99%

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

et al. 2017

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An inspiring UTBB SOI MOSFET structure with enhanced immunity to the drain-induced barrier lowering (DIBL) is analyzed. The structure includes the dual-gates in the lateral direction. The voltage difference is applied between the dual-gates, through which the electrostatic potential and the energy band along the channel are modified and the electrical performance is boosted. The electrical characteristics are investigated by measuring the electron concentration, the conduction band energy level, and the potential at the front-surface. The impact of the negative voltage bias applied to the right gate on the performance of the new device is studied, and compared to that of the conventional ultra-thin body ultra-thin box silicon-on-insulator (UTBB SOI) devices. The results reveal that the undesirable DIBL values are lower in this innovative device than that in the conventional UTBB SOI MOSFET.

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Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

Cited by 45 publications

References 33 publications

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

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