Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

Wei, Sufen; Zhang, Guohe; Shao, Zili; Geng, Li; Yang, Cheng-Fu

doi:10.1007/s00542-017-3532-4

Cited by 15 publications

(5 citation statements)

References 19 publications

(19 reference statements)

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“…Silicon-based metal oxide semiconductor field-effect transistors (MOSFETs) have been widely used in the last few decades. However, as the channel length has been shrinking, short channel effects [ 1 , 2 ] have emerged and decreased the device’s precision. Two-dimensional (2D) materials have emerged as promising candidates to tackle these issues.…”

Section: Introductionmentioning

confidence: 99%

Modeling the Impact of Phonon Scattering with Strain Effects on the Electrical Properties of MoS2 Field-Effect Transistors

et al. 2023

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Molybdenum disulfide (MoS2) has distinctive electronic and mechanical properties which make it a highly prospective material for use as a channel in upcoming nanoelectronic devices. An analytical modeling framework was used to investigate the I–V characteristics of field-effect transistors based on MoS2. The study begins by developing a ballistic current equation using a circuit model with two contacts. The transmission probability, which considers both the acoustic and optical mean free path, is then derived. Next, the effect of phonon scattering on the device was examined by including transmission probabilities into the ballistic current equation. According to the findings, the presence of phonon scattering caused a decrease of 43.7% in the ballistic current of the device at room temperature when L = 10 nm. The influence of phonon scattering became more prominent as the temperature increased. In addition, this study also considers the impact of strain on the device. It is reported that applying compressive strain could increase the phonon scattering current by 13.3% at L = 10 nm at room temperature, as evaluated in terms of the electrons’ effective masses. However, the phonon scattering current decreased by 13.3% under the same condition due to the existence of tensile strain. Moreover, incorporating a high-k dielectric to mitigate the impact of scattering resulted in an even greater improvement in device performance. Specifically, at L = 6 nm, the ballistic current was surpassed by 58.4%. Furthermore, the study achieved SS = 68.2 mV/dec using Al2O3 and an on–off ratio of 7.75 × 104 using HfO2. Finally, the analytical results were validated with previous works, showing comparable agreement with the existing literature.

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Section: Introductionmentioning

confidence: 99%

Modeling the Impact of Phonon Scattering with Strain Effects on the Electrical Properties of MoS2 Field-Effect Transistors

et al. 2023

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“…For TFT 0 , due to the high potential gradient caused by the applied drain bias, more holes can drift from the source to the drain and give a high drain current. Notably, for TFT R+1 , the extra barrier Ф R+1 is nearly absent, which is because of the field-induced barrier lowering effect [31,32]. The significant reduction in this extra barrier explains the significant reduction in the performance degradation of TFT R+1 at the higher V DS of −10 V (figure 5(b)).…”

Section: Effect Of Offsets Of An Individual Ur On the Tft Performancementioning

confidence: 98%

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

Hsu¹,

Chen²

2019

Semicond. Sci. Technol.

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In this paper, electrical characteristics of dual-gate polycrystalline silicon (poly-Si) thin film transistors (TFTs) with different undoped region (UR) offsets are investigated. Performance degradation of the poly-Si TFT is dependent on the offset value, offset direction, and offset location. In addition, the degradation is also dependent on the applied drain bias. Significant performance deterioration is observed when the offset is larger than ±0.4 μm. Even an offset in an individual UR can cause the degradation. At a low drain bias of −0.1 V, the degradation is independent on the direction and the location of the offset. When the drain bias increases to −10 V, the performance degradation of the TFT with the positive UR offset significantly reduces. The physical mechanisms underlying the performance variation are studied by analyzing the energy band diagrams, carrier concentration distributions, and electric field distributions.

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“…These process steps were partially sourced from [15]. In figure 2(a), we consider the silicon substrate and oxidize it to form a 10 nmthick SiO 2 (BOX) layer on the silicon body [16]. On top of the BOX, we deposited a Si layer whose height was equal to the height of the pocket, that is, P w and doped it with acceptor atoms using the ion implant process.…”

Section: Device Processing Stepsmentioning

confidence: 99%

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

Singh,

Mishra,

Akhter

2024

Eng. Res. Express

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This study investigates the electrical performance of advanced semiconductor Ge-pocket-doped fully depleted silicon-on-insulator MOSFETs in comparison to conventional fully depleted silicon-on-insulator (FDSOI) MOSFETs. In this study vital electrical parameters such as the drain current, band diagram, lateral electric field, surface potential, and work function of the gate material were investigated. The advanced Ge pocket-doped FDSOI MOSFET structure demonstrates superior characteristics, such as a higher Ion/Ioff ratio, smaller subthreshold slope, lower capacitance, and higher cut-off frequency, when compared to conventional FDSOI MOSFETs. The structure of the Ge pocket-doped FDSOI MOSFET in the source and drain regions is designed to overcome the scaling effects of the transistor. In addition, this paper delves into the fabrication of the proposed device structure, outlining the key steps and intricacies involved. This study shows that the proposed device can be used for both digital and analog applications because it has good switching performance and a low cut-off frequency. In addition, the fabrication steps of the proposed structure were compatible with the existing fabrication process steps for conventional FDSOI MOSFETs. The simulation and analysis of the advanced semiconductor structure were performed using the Sentaurus TCAD simulator.

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Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

Cited by 15 publications

References 19 publications

Modeling the Impact of Phonon Scattering with Strain Effects on the Electrical Properties of MoS2 Field-Effect Transistors

Modeling the Impact of Phonon Scattering with Strain Effects on the Electrical Properties of MoS2 Field-Effect Transistors

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

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