We have developed a 36-inch surface-conduction electron-emitter display (SED), consisting of surface conduction electron emitters (SCEs) and a phosphor screen for CRTs. The main features of the prototype are luminance of 400 cd/m 2 , contrast ratio of 10,000: 1 in a dark room, and response time of <1 ms. The SED panel offers sufficient performance for application to TVs.

Abstract— A surface‐conduction electron emitter (SCE) for next‐generation flat‐panel displays has been developed. PdO thin films (approximately 10 nm thick) produced by an ink‐jet process were used to form the surface‐conduction electron emitter. The films were electroformed and activated while a voltage was applied, and an electron emitter with good characteristics was obtained. A current density of approximately 30 mA/cm2 was attained when an anode voltage of 10 kV was applied. Furthermore, a 36‐in. surface‐conduction electron‐emitter display (SED), consisting of SCEs and a phosphor screen similar to that of a CRT, was also developed.

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The Back Enhanced SOI (BESOI MOSFET) is a planar reconfigurable device, which transistor type (n- or p-type) can be programed by the back-gate bias. This transistor is explored in this paper for biosensing application through numerical simulation, based on the fabricated device experimental results. The permittivity value and the charges inside the biomaterial deposited on the underlap region (between gate and source/drain contacts) influence the BESOI MOSFET drain current. The dimensions of the device were evaluated in order to optimize the sensitivity. Among the studied parameters, the underlap length was the most relevant parameter. For short underlap devices, the fringe electric field from the front gate electrode benefits the permittivity-based sensors, while long underlap length devices have a bigger sensitive area in which the charge-based sensor presented better results. Also, the n-type biased device presented higher sensitivity to positively charged materials, while the p-type biased one presented better result for negatively charged materials. The parameters optimization resulted in one order magnitude improvement of the sensitivity for the permittivity-based sensor, for both n- and p-type. As for the charge-based sensor, the optimized device presented twice as bigger sensitivity for the n-type, and at least eight times improvement for the p-type device. This fact represents an advantage of the BESOI structure as the type of the device can be chosen by the back-gate bias.

This paper investigates the ground plane influence on Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT) operation (V B =V G ) over the conventional one (V B =0V). The ground plane in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (V B =k×V G ), and the inverse eDT mode (V G =k×V B ) were also considered and compared to the other configurations. The presence of the Ground Plane region in all DT configurations results in superior DC parameters like oncurrent/off-current ratio, a steeper subthreshold slope and a higher transconductance.

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