Silicon film thickness influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Sasaki, K. R. A.; Aoulaiche, M.; Simoen, Eddy; Claeys, Cor; Martino, João Antônio

doi:10.1109/sbmicro.2014.6940089

Cited by 6 publications

(8 citation statements)

References 15 publications

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“…The study and analytical modeling of the influence of a GP was reported in [6][7][8]. Moreover, the presence of a GP on the Dynamic Threshold operation mode was studied and modeled in [9][10][11]. The analog performance was reported in [12] where the GP influence was studied for the analog figures of merit and in [13][14] where an initial study of the same devices presented in this paper was done.…”

Section: Introductionmentioning

confidence: 99%

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Itocazu¹,

Sonnenberg²,

Martino³

et al. 2020

JICS

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This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

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Section: Introductionmentioning

confidence: 99%

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Itocazu¹,

Sonnenberg²,

Martino³

et al. 2020

JICS

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“…Some optimizations have been reported about this approach, regarding the ground plane and the channel length influence in these operation modes [19] or the impact of the silicon film thickness [20]. The effect of the buried oxide thickness on the analog figures of merits has been studied [20][21][22][23], as well as the circuit for generating the back gate of the eDT mode for a sleep transistor, taking into account the back gate capacitance influence on the circuit performance. Finally, the application of the dynamic threshold technique in UTBB devices as a power switch has also been discussed [24].…”

Section: Introductionmentioning

confidence: 99%

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

Sasaki

Aoulaiche

Simoen

et al. 2015

JLPEA

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This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold

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“…Fonte: [74] Observa-se, como esperado, uma redução da tensão de limiar para maiores valores de k, devido ao efeito DT, e para filmes mais espessos da camada de silício, devido ao melhor acoplamento da porta e do substrato sobre o canal. Uma vez que o tSi é muito fino, o potencial do canal necessário para se atingir a inversão é maior [12].…”

Section: Dt2 Kdtunclassified

“…Vê-se também que, para maiores valores de k, a diferença entre as tensões de limiar para as duas espessuras do filme de silício estudadas é desprezível. [74] 4.…”

Section: Dt2 Kdtunclassified

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Estudo de transistores SOI MOSFETs com camada de silício e óxido enterrado ultrafinos operando em modo de tensão de limiar dinâmica.

Sasaki¹

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Gostaria de agradecer ao Profº Dr. João Antonio Martino pela orientação, pelos ensinamentos, pelo constante incentivo transmitido ao longo de todo o trabalho e pela confiança depositada. Agradeço à FAPESP, pelo apoio financeiro prestado aqui no Brasil e no exterior. Agradeço também aos meus pais, Mitsue e Pedro, sem os quais não teria chegado aqui, à minha irmã, Karen, e a todos os meus familiares que me apoiaram e ajudaram. Aos grandes amigos e co-autores Luciano, Sara, Talitha, Tatsuo e Albert, que me apoiaram e ajudaram, durante o mestrado e, agora durante o doutorado, eu não poderia deixar de lhes agradecer por tudo o que aprendi junto deles, por toda a paciência prestada e por todo o apoio e auxílio também agora, no doutorado. Ao grande amigo Matheus pela ajuda com as primeiras medidas deste trabalho, além do grande incentivo, amizade, discussões, aprendizado conjunto, paciência e dedicação. Aos também grandes amigos Rangel, Caio, Alberto, Ferrari e Felipe pelo aprendizado conjunto, pelas muitas discussões, paciência, incentivos e amizade. Ao Marc Aoulaiche, Eddy Simoen, Cor Claeys pelo fornecimento de lâminas e pelas discussões e revisões de nossos artigos. Ao Profº Sorin Cristoloveanu, Maryline Bawedin e Carlos Navarro pelo fornecimento de lâminas, discussões, revisões de nossos artigos e auxílio durante o estágio realizado no MINATEC, Grenoble, França. Também ao Gustavo Rehder com a ajuda prestada na viagem para Grenoble. Ao meu noivo Ygor pela compreensão, paciência, incentivo, companhia e amizade. A todos do grupo SOI e do MINATEC que ajudaram de alguma forma nesse trabalho e que, de forma involuntária, foram aqui omitidos.

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Silicon film thickness influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Cited by 6 publications

References 15 publications

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

Estudo de transistores SOI MOSFETs com camada de silício e óxido enterrado ultrafinos operando em modo de tensão de limiar dinâmica.

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