Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Sasaki, K. R. A.; Manini, M.; Martino, João Antônio; Aoulaiche, M.; Simoen, Eddy; Witters, L.; Claeys, Cor

doi:10.1109/iccdcs.2014.7016149

Cited by 11 publications

(7 citation statements)

References 12 publications

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“…The study and analytical modeling of the influence of a GP was reported in [6][7][8]. Moreover, the presence of a GP on the Dynamic Threshold operation mode was studied and modeled in [9][10][11]. The analog performance was reported in [12] where the GP influence was studied for the analog figures of merit and in [13][14] where an initial study of the same devices presented in this paper was done.…”

Section: Introductionmentioning

confidence: 99%

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Itocazu¹,

Sonnenberg²,

Martino³

et al. 2020

JICS

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This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

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Section: Introductionmentioning

confidence: 99%

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Itocazu¹,

Sonnenberg²,

Martino³

et al. 2020

JICS

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“…In UTBB FDSOI devices, the concept of dynamic threshold mode cannot be the same as for PDSOI, due to the absence of a floating body contact. The solution for FDSOI devices, in order to apply the dynamic technique, is to connect the front gate with the back gate (substrate) [7,8]. Therefore, this technique can be applied in a promising device, with the advantages of a stronger V GB coupling and the buried oxide isolation, allowing V GF higher than 0.7V.…”

Section: Introductionmentioning

confidence: 99%

Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation

Itocazu¹,

Sasaki²,

Sonnenberg³

et al. 2020

JICS

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This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

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“…However, the bulk-drain junction can be forward biased if the gate voltage is higher than 0.7 V, which is a disadvantage for these devices. Recently, with the advent of UTBB devices, a new generation of dynamic threshold voltage configuration (DT2) has been studied [3,18]. In this case, the front gate is connected to the back-gate and the same concept is achieved: during the VG sweep, the threshold voltage (VT) is dynamically reduced, as it is a function of the VBody (in PDSOI) or VB (in UTBB), which is equal to VG, improving the device performance [17].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the goal of this work is to compare the impact of the underlap length (LUL), including the self-aligned devices (LUL = 0 nm), on UTBB SOI MOSFETs when submitted to a conventional and a dynamic threshold voltage (DT2) configuration, focusing on low power low voltage applications. In order to enhance the back gate influence on VT, a back gate bias with a multiple value of the front gate voltage (VB = k × VG) is also used [3,18], with k > 1, which is called the eDT mode in this paper. Figure 2 shows the structure of an extensionless UTBB FDSOI device.…”

Section: Introductionmentioning

confidence: 99%

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

Sasaki

Aoulaiche

Simoen

et al. 2015

JLPEA

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This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold

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Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Cited by 11 publications

References 12 publications

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

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