Sub-0.18 μm SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology

Cheng, Baolei; Rao, V. Ramgopal; Woo, J.C.S.

doi:10.1109/soi.1998.723137

Cited by 16 publications

(18 citation statements)

References 1 publication

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“…Recently, asymmetric single halo (SH) MOSFET structures have been introduced for bulk [54][55] as well as for SOI MOSFETs [56][57] to adjust the threshold voltage and improve the device SCE and hot carrier effects (HCE). These devices also achieve higher drive currents by exploiting the velocity overshoot phenomenon [54], which is an advantage in mixed mode analog/digital circuits.…”

Section: Halo Doped Soimentioning

confidence: 99%

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Chaudhry

Kumar

2004

IEEE Trans. Device Mater. Relib.

386

134

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This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

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Section: Halo Doped Soimentioning

confidence: 99%

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Chaudhry

Kumar

2004

IEEE Trans. Device Mater. Relib.

386

134

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“…The devices had a source/drain extension in addition to deep source/drain junction. A two-step titanium silicidation process with Ge pre-amorphization was used to control the silicide depth and reduce the contact resistance [7]. Fig.…”

Section: Device Fabricationmentioning

confidence: 99%

“…Channel engineering has been widely used to improve the short-channel performance. Asymmetric single halo (SH) MOSFET structures have been introduced for bulk [5], [6] as well as for SOI MOSFETs [7], [8] to adjust the threshold voltage and improve the device SCE and hot carrier effects (HCEs). These devices also achieve higher drive currents by exploiting the velocity overshoot phenomenon [5], which is an advantage in mixed-mode analog/digital circuits.…”

mentioning

confidence: 99%

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

Hakim

Rao

Vasi

et al. 2005

IEEE Trans. Device Mater. Relib.

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Abstract-In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better th -roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain ( ) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.Index Terms-Channel hot carrier, mixed-signal applications, silicon-on-insulator technology, single halo, thin film devices.

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“…The devices had a source/drain extension in addition to deep source/drain junction. A two-step titanium silicidation process with Ge preamorphization was used to control the silicide depth and reduce the contact resistance [8]. Fig.…”

Section: Fabricationmentioning

confidence: 99%

“…Channel engineering has been widely used to improve the short channel performance. Asymmetric single halo MOSFET structures have been introduced for bulk [6][7] as well as for SOI MOSFETs [8][9] to adjust the threshold voltage and improve the device SCE and hot carrier effects (HCE). These devices also achieve higher drive currents by exploiting the velocity overshoot phenomenon [6], which is an advantage in mixed mode analog/digital circuits.…”

Section: Introductionmentioning

confidence: 99%

Small signal characteristics of thin film single halo SOI MOSFET for mixed mode applications

Hakim

Rao

Vasi

16th International Conference on VLSI Design, 2003. Proceedings.

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Sub-0.18 μm SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology

Cited by 16 publications

References 1 publication

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

Small signal characteristics of thin film single halo SOI MOSFET for mixed mode applications

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