Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Abstract

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

“…This increases the number of carriers injected into the channel from the source leading to an increased drain off-current as shown in Figure 7. Thus, the drain current is controlled not only by the gate voltage, but also by the drain voltage [11].…”

Characteristic Analysis of Dual Gate Metal Oxide Semiconductor Field Effect Transistor by Mathematical Modeling

“…It is well known that the short-channel effects are remarkably reduced in SOI films. Since bulk MOSFETs are expected to reach their limit for gate lengths below 30 nm (Chaudhry and Kumar, 2004;Brown et al, 2002), alternative architectures have been proposed to overcome their limitations. The DoubleGate (DG) transistor is considered one of the most promising devices for extremely scaled CMOS technology generations (Widiez et al, 2005).…”

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

“…DG MOSFETs will probably be planar, extremely thin for volume inversion and fabricated with a bonding technology as reported in Scott Thompson et al and G. K. Cellera et al [4,5]. As CMOS scaling approaches the limit the DG-MOSFET has its ability to be scaled to sub 100 nm with better performance, excellent SCEs immunity, higher drain current, volume inversion (VI), higher trans-conductance and steeper sub-threshold slope have been reported by various studies [6][7][8][9][10][11][12][13]. Scaling down improves cut off frequency due to the reduction of supply voltage the analog performance degrades due to SCEs.…”

“…Scaling down improves cut off frequency due to the reduction of supply voltage the analog performance degrades due to SCEs. Efficient Gate Engineering & Channel Engineering for sub-100nm devices are a major challenge reported by Bin Yu et al and Biswajit Ray et al [13,14].. In the past few years, the local high doping concentration in the channel near source/drain junctions have been implemented via lateral channel engineering, e.g.…”