Small signal characteristics of thin film single halo SOI MOSFET for mixed mode applications

Hakim, Najeeb-ud-din; Rao, V. Ramgopal; Vasi, J.

doi:10.1109/icvd.2003.1183123

Cited by 6 publications

(8 citation statements)

References 14 publications

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“…The other advantages of SH over CON SOI MOSFETs, such as absence of kink, lower inherent parasitic bipolar junction transistor (pBJT) gain have also been reported elsewhere in detail [12], [13]. The superior small-signal characteristics for mixed-mode applications of deep-submicron thin film SH SOI MOSFETs have also been reported in detail [14].…”

mentioning

confidence: 81%

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

Hakim

Rao

Vasi

et al. 2005

IEEE Trans. Device Mater. Relib.

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Abstract-In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better th -roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain ( ) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.Index Terms-Channel hot carrier, mixed-signal applications, silicon-on-insulator technology, single halo, thin film devices.

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confidence: 81%

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

Hakim

Rao

Vasi

et al. 2005

IEEE Trans. Device Mater. Relib.

Self Cite

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“…Also shown in the same enclosed plot are the actual measured values for VT SC , as reported in Ref. .…”

Section: Experimental Data and Model Simulationsmentioning

confidence: 94%

“…Figure also contains a smaller plot (inset) that shows a simulation describing the trend of VT SC in a different FD‐SOI MOSFET presented in Ref. that also incorporated HALO. The simulated VT SC used the exact process constants and dimensions specified in Ref.…”

Section: Experimental Data and Model Simulationsmentioning

confidence: 94%

“…The simulated VT SC used the exact process constants and dimensions specified in Ref. . Also shown in the same enclosed plot are the actual measured values for VT SC , as reported in Ref.…”

Section: Experimental Data and Model Simulationsmentioning

confidence: 99%

“…( φ Fms = −0.65 V, φ pFms = −0.8 V, and φ Bms = −0.75 V were utilized in simulating VT SC in the device) …”

Section: Experimental Data and Model Simulationsmentioning

confidence: 99%

See 2 more Smart Citations

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

Tarakji

2018

Physica Status Solidi (a)

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No models exist for fully depleted silicon-on-insulator (FD-SOI) metal-oxidesilicon field-effect-transistors (MOSFETs) that operate at high currents and voltages. Operation at high currents and voltages dictates the radio-frequency (rf ) output power that such devices can deliver and transmit from the particular rf-integrated circuits used in today's cellular phones. In this work, a first order dc model for FD-SOI MOSFETs that are specifically designated to operate at high biases and large rf swings is presented. These devices typically incorporate HALO and body-tied-source (BTS), which enable much higher biases to be applied to the gate and drain and allow larger rf swings. They also employ dual-gated designs that further reduce the threshold voltage and increase the current. Although the newly established model accurately replicates the general dc behavior of any FD-SOI MOSFET that incorporates HALO and BTS, it is specifically tailored to an innovative and recently patented device structure for FD-SOI MOSFET. The new structure adopts an improved and unique design for BTS and HALO that most effectively filters the impact-ionization current to BTS and improves the device performance. New design rules that enable the designs of areaefficient layouts for FD-SOI MOSFETs that incorporate the HALO and BTS are also presented. status solidi physica a Field-Effect-Transistors www.pss-a.com

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Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

Patil

2020

Eng. Res. Express

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In this work two dimensional sentaurus simulations are used to study the impact of substrate doping on scalability and the variability of the bulk planar junctionless transistor (BPJLT). The results shows that, although increasing substrate doping density in BPJLT reduces the off-state current, subthreshold slope and the drain induced barrier lowering, the on-state current of the device is almost constant. To improve digital logic circuit performance of nanoscale BPJLT, novel δ-layer BPJLT (δ-BPJLT) is being proposed by incorporating p-type δlayer below the uniformly doped device layer containing source, channel and the drain regions of BPJLT. It has been found that, the δ-layer below the device layer leads to reduction in the off-state current, process induced variability and the short-channel effects of the BPJLT. This is mainly because of the screening effect due to δ-layer under the device layer which significantly reduces the variations induced because of random dopant fluctuations.

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Small signal characteristics of thin film single halo SOI MOSFET for mixed mode applications

Abstract: In this paper we report a study on

Cited by 6 publications

References 14 publications

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

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