Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Paz, Bruna Cardoso; Cassé, M.; Barraud, S.; Reimbold, G.; Vinet, M.; Faynot, O.; Pavanello, Marcelo Antonio

doi:10.1016/j.sse.2016.10.023

Cited by 11 publications

(8 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One group consisted of measured experimental nanowire and nanosheet transistors fabricated by CEA-Leti [6,20] and the other were simulated transistors. Experimental transistors were measured at 25 • C and fabricated in SOI substrates with 145 nm thick buried oxide.…”

Section: Sddgm Model Validation For Nanowires and Nanosheetsmentioning

confidence: 99%

“…A special FinFET structure with three gates, when the transistor fin height (H FIN ) and fin width (W FIN ) have similar dimensions, is known as nanowire, as depicted in figure 1(a). These 3D nanowire structures have been extensively studied [4][5][6]. Now, for a new generation of integrated circuits, a new MOSFET structure known as nanosheet, presented in figure 1(b), is under development, which is a four-gate or a gate-all-around (GAA) transistor.…”

Section: Introductionmentioning

confidence: 99%

“…Now, for a new generation of integrated circuits, a new MOSFET structure known as nanosheet, presented in figure 1(b), is under development, which is a four-gate or a gate-all-around (GAA) transistor. These nanowire and nanosheet transistors can be stacked, as shown in figure 1(c), to increase the total current [6][7][8][9] in the same transistor floor plan.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Cerdeira¹,

Estrada²,

Pavanello³

2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

In this paper, 3D TCAD simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in Nanowire and Nanosheet structures, are practically same. This characteristic makes possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend the application of the Symmetric Doped Double-Gate Model (SDDGM) model to Nanowires and Nanosheets MOSFETs, with no need to include new parameters. The Model SDDGM is validated for this application using several measured and simulated structures of Nanowires and Nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SmartSPICE circuit simulator.

show abstract

Section: Sddgm Model Validation For Nanowires and Nanosheetsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Cerdeira¹,

Estrada²,

Pavanello³

2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…The influence of strain on the electrical characteristics of SOI nanowires has been studied as well [22]. Figure 6 presents the extracted effective carrier mobility as a function of VGT, obtained with drain bias of 40 mV and different WFIN values, for L=10 µm SOI and sSOI nanowires at room temperature.…”

Section: A Operation At 300 Kmentioning

confidence: 99%

Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures

Pavanello

Souza

2022

JICS

View full text Add to dashboard Cite

This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.

show abstract

“…Mobility is a key quantity in electronic transport that provides an understanding of the physical processes affecting the motion of free carriers [1][2][3][4]. Comparative analysis of mobility as a key figure of merit of heterosystems is of great importance in synthesizing novel materials, developing novel thin-film technologies, interface modification, controlling fabrication of films and devices on their base [5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Conditions for the identical distribution of free carriers in thin films

Zaytseva¹,

Naumova²,

Гутаковский³

2021

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

The condition of the same distribution of free carriers in thin films is necessary for comparing the mobility and analyzing the scattering mechanisms of carriers near semiconductor film/insulator interfaces. In thin film/insulator systems with different design parameters, it is difficult to ensure the same distribution of free carriers due to physical phenomenon such as the coupling effect. In this study, TCAD simulations of thin-film transistors, which have been used to monitor Si film properties, were applied to find parameters that allow tuning the potential distribution and, accordingly, the distribution of free carriers in films. It was found that such parameters are the film regime, the density of induced carriers, the gate voltage or threshold voltage of transistors. The conditions for the selection of parameters were found that ensure the same distribution of free carriers in thin-film structures for the cases of different thicknesses of films and the surrounding dielectrics. It was shown that the proposed approach can be used for a comparative analysis of the mobility in thin films and makes it possible to eliminate errors associated with different distributions of carriers in the films due to the coupling effect.

show abstract

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Cited by 11 publications

References 20 publications

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures

Conditions for the identical distribution of free carriers in thin films

Contact Info

Product

Resources

About