Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures

Abstract

This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

“…The rate of variation of the threshold voltage with temperature (dVTH/dT) is shown in Table I for both VDS values. The improved potential coupling caused by fin width reduction is also responsible for the slight decrease in the |dVTH/dT| rate [25]. For all devices, the increase of drain bias leads to the reduction of VTH due to drain-induced barrier lowering, which becomes more pronounced as the temperature is raised, as presented in Fig.…”