High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Abstract

In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

“…The experimental analysis of nanowire MOS transistors at high temperatures was presented in references 22–24. In these works, one can see the influence of several tunneling components on the device output characteristics.…”