Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Souza, Michelly de; Cerdeira, A.; Estrada, M.; Cassé, M.; Barraud, S.; Vinet, M.; Faynot, O.; Pavanello, Marcelo Antonio

doi:10.1016/j.sse.2023.108716

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Analytical Models For the Drain And Gate Currents Of Nanowir...1

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2024

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“…The experimental analysis of nanowire MOS transistors at high temperatures was presented in references 22–24. In these works, one can see the influence of several tunneling components on the device output characteristics.…”

Section: Analytical Models For the Drain And Gate Currents Of Nanowir...mentioning

confidence: 99%

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

Cerdeira,

Estrada,

de Souza

et al. 2024

Int J Numerical Modelling

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This work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain‐to‐channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high‐temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high‐temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement.

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Section: Analytical Models For the Drain And Gate Currents Of Nanowir...mentioning

confidence: 99%

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

Cerdeira,

Estrada,

de Souza

et al. 2024

Int J Numerical Modelling

Self Cite

View full text Add to dashboard Cite

show abstract

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

de Souza,

Cerdeira,

Estrada

et al. 2024

Solid-State Electronics

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Cited by 2 publications

References 12 publications

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

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