On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Abstract

In this paper, 3D TCAD simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in Nanowire and Nanosheet structures, are practically same. This characteristic makes possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend the application of the Symmetric Doped Double-Gate Model (SDDGM) model to Nanowires and Nanosheets MOSFETs, with no need to include new parameters. The Model SDDGM is validated for this application using several measured and simulated structures of Nanowires and Nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SmartSPICE circuit simulator.

Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

“…For correcting the maximum mobility variation with temperature, expression (4) is applied 18 : $$$$ {\mu}_{0\mathrm{EF}}=\frac{\mu_0}{{\left(\frac{T}{300}\right)}^{\xi }}, $$$$ where ξ is a thermal mobility factor used as an adjusting parameter.…”

“…In references 17,18, an analytical model for the drain current ( I DS ) as a function of the applied voltages at the gate ( V GS ) and drain ( V DS ) terminals of nanowire MOS transistors has been proposed and validated at room temperature. In this model, the drain current is a function of the mobile charges at the source and drain ends of the channel ( q ns and q nd , respectively), normalized by C i kT/q , where $$$ {C}_{\mathrm{i}}={\varepsilon}_{\mathrm{ox}}/{t}_{\mathrm{ox}} $$$ is the gate insulator capacitance per unit area, ε ox is the oxide permittivity, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge: $$$$ {I}_{\mathrm{DS}}=\frac{2\frac{W}{L}{C}_{\mathrm{i}}\ \frac{k\ T}{q}\ {\mu}_{\mathrm{s}}}{\left(1-\frac{\Delta L}{L}\right)}\frac{\frac{1}{2}\left({q}_{\mathrm{ns}}^2-{q}_{\mathrm{nd}}^2\right)+{\left[2\left({q}_{\mathrm{ns}}-{q}_{\mathrm{nd}}\right)-{q}_{\mathrm{b}}\ln \left(\frac{q_{\mathrm{ns}}+{q}_{\mathrm{b}}}{q_{\mathrm{nd...$$…”

“…Amongst them, we developed the symmetric doped double‐gate model (SDDGM) for FinFETs, which was validated experimentally and encoded in Verilog‐A language for circuit simulations 16,17 . Besides, in reference 18, we demonstrated that the SDDGM can also be used to model the drain current of silicon‐on‐insulator (SOI) nanowires and nanosheet MOS transistors at room temperature with very good agreement. The application of the SDDGM model to nanowires and nanosheets is possible because the electric field distribution, from the interfaces at the sidewall channels and from the top channel to the center of the silicon fin in both nanowire and nanosheet structures, follows the same law as in FinFETs.…”

“…This work intends to present a complete analytical model for SOI nanowires and nanosheets, valid in a wide temperature range of temperatures higher than room temperature. With this objective, initially, we present the extension of the analytical model for the drain current of SOI nanowires and nanosheets given in reference 18 to high temperatures in the range from 300 to 500 K. Also, this work will present the analytical model of the gate current, valid in subthreshold and above threshold regions of operation in the same temperature range. The manuscript is organized as follows: Section 2 presents the model equations describing nanowires' drain current at high temperatures.…”

“…Additionally, the models for the gate current components, the junction leakage current, and the Gate‐Induced Drain Leakage are introduced, completing the analytical model proposed in reference 18. These current components will be used in the devices analysis and discussion.…”