Structural analysis and generation of synthetic digital circuits with memory

Wilton, Steven J. E.; Rose, Jonathan; Vranesic, Z.G.

doi:10.1109/92.920838

Cited by 8 publications

(6 citation statements)

References 27 publications

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“…The authors claim that the generated clones deviated from their original counterparts by less than 17%. Another clone-based approach was presented by Wilton et al [29]. They first performed a thorough study of real-world circuits with combinational logic and memory interconnections to characterize them for various number, size, and shapes of memories.…”

Section: Existing Sbc Generation Methodsmentioning

confidence: 98%

Synthetic benchmark digital circuits: A survey

Srivani¹,

Kamakoti²

2012

IETE Tech Rev

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Today's VLSI CAD tools are to be designed to handle tomorrow's designs. But, what are tomorrow's designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware architects including those who design processors and FPGAs. For the VLSI CAD tool and FPGA architects, the synthetic benchmark circuits (SBCs) come to their rescue by providing representative designs of tomorrow. This paper elaborates on the various techniques reported in the literature for generation of SBCs. It also presents a case study of generating a SBC for accelerated life testing of an FPGA. The paper concludes posing interesting open issues in this field.

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Section: Existing Sbc Generation Methodsmentioning

confidence: 98%

Synthetic benchmark digital circuits: A survey

Srivani¹,

Kamakoti²

2012

IETE Tech Rev

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“…Previous work in synthetic circuit generation for reconfigurable architectures generally focuses on the use of LUTs [5,6,7,8]. However, the architectures generation algorithms that will be tested here are much more coarse-grained in nature, using wordwidth ALUs, multipliers, and other large logical units.…”

Section: Circuit Generatormentioning

confidence: 99%

Flexibility measurement of domain-specific reconfigurable hardware

Compton

Hauck

2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

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Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For these designs, flexibility is also a key issue, since it is the flexibility of reconfigurable hardware that allows it to implement a variety of circuits. Despite its importance, there is not yet an established method to measure flexibility. This paper explores the flexibility testing issue for domain-specific reconfigurable architectures. We discuss the concept of flexibility as it pertains to domain-specific architectures, and propose a flexibility testing technique involving synthetic circuit generation. This technique is then used to compare three different domain-specific architecture generation algorithms, demonstrating that the testing can in fact differentiate between architectures of differing levels of flexibility.

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“…A number of other synthetic circuit generators have recently been proposed in the literature [9,[11][12][13][14][15][16][17][18][19], which we will now review.…”

Section: Other Synthetic Generation Effortsmentioning

confidence: 99%

“…Wilton et al [17] generate synthetic circuits with both logic and memory. Their method of generation is, first, to characterize large numbers of real circuits with a view to how logic and memory interconnect and the number, size, and shapes of the memories.…”

Section: Other Synthetic Generation Effortsmentioning

confidence: 99%

Synthetic Circuit Generation Using Clustering and Iteration

Kundarewich

Rose

2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The development of next-generation CAD tools and FPGA architectures require benchmark circuits to experiment with new algorithms and architectures. There has always been a shortage of good public benchmarks for these purposes, and even companies that have access to proprietary customer designs could benefit from designs that meet size and other particular specifications. In this paper, we present a new method of generating realistic synthetic benchmark circuits to help alleviate this shortage. The method significantly improves the quality of previous work by imposing a hierarchy of circuits through clustering and by using a simpler method of characterizing the nature of sequential circuits. Also, in contrast to current constructive generation methods [7-9,11-16,18,19], we employ new iterative techniques in the generation that provide better control over the generated circuit's characteristics. As in previous work, we assess the realism of the generated circuits by comparing properties of real circuits and generated "clones" of the real circuit after placement and routing. On average, the real and clone circuits' total detailed wirelength differ by only 14%, a major improvement over previous results. In addition, the minimum track count is within 14% and the critical path delay is within 10%.

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Structural analysis and generation of synthetic digital circuits with memory

Cited by 8 publications

References 27 publications

Synthetic benchmark digital circuits: A survey

Synthetic benchmark digital circuits: A survey

Flexibility measurement of domain-specific reconfigurable hardware

Synthetic Circuit Generation Using Clustering and Iteration

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