Synthetic Circuit Generation Using Clustering and Iteration

Kundarewich, Paul D.; Rose, Jonathan

doi:10.1109/tcad.2004.828132

Cited by 25 publications

(7 citation statements)

References 19 publications

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“…Alternatively, we could have used synthetic-circuit generating techniques [7,8,13]. These techniques are good for cloning existing circuits: they typically work by top-down partitioning or bottom-up clustering of modules and adding nets between the modules while enforcing stochastic interconnect parameters.…”

Section: Benchmark Creationmentioning

confidence: 99%

Logic block clustering of large designs for channel-width constrained FPGAs

Tom¹,

Lemieux²

2005

Proceedings. 42nd Design Automation Conference, 2005.

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In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2,3,11] aim to reduce the amount of inter-cluster connections, hence reducing channel width needs. However, if this exceeds the FPGA's channel width (a hard constraint), then the circuit still cannot be routed. Previous work [11,12] depopulates logic clusters (CLBs) to reduce channel width. By depopulating non-uniformly, i.e. depopulate more in hard-to-route regions, we show a graceful trade-off between channel width and CLB count. This makes it possible to target specific channel-width constraints during clustering with minimal CLB inflation. Results show channel width decreases of up to 20% with a 5% increase in area. Further decreases of nearly 50% are possible at 3.3 times the original area. Despite the area increase, this technique creates routable solutions from otherwise-unroutable circuits.

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Section: Benchmark Creationmentioning

confidence: 99%

Logic block clustering of large designs for channel-width constrained FPGAs

Tom¹,

Lemieux²

2005

Proceedings. 42nd Design Automation Conference, 2005.

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“…In addition, a synthetic benchmark circuit generator based on [19] is used. The generator can produce floating-point circuits from a characterization file describing circuit and cluster statistics.…”

Section: A Benchmark Circuitsmentioning

confidence: 99%

Floating-Point FPGA: Architecture and Modeling

Leong

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point operations are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block scheme is proposed to model embedded blocks using existing field-programmable gate array (FPGA) tools. This methodology involves adopting existing FPGA resources to model the size, position, and delay of the embedded elements. The standard design flow offered by FPGA and computer-aided design vendors is then applied and static timing analysis can be used to estimate the performance of the FPGA with the embedded blocks. On selected floating-point benchmark circuits, our results indicate that the proposed architecture can achieve four times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.

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“…A number of methods exist to create synthetic circuits including stochastic generation using just a few parameters (e.g., gnl [1]), stochastic generation of clones based upon detailed characterization of real circuits (e.g., ccirc+cgen [2,3]), and stochastic stitching together of real designs as subcircuits of a larger design [4,5]. Ultimately, these generators are concerned with creating an entire benchmark circuit, making them unsuitable for creating incremental circuits where large parts of the circuit must remain the same.…”

Section: Introductionmentioning

confidence: 99%

Semi Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

Grant

Chin

Lemieux

2006

2006 International Conference on Field Programmable Logic and Applications

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FPGA architects are always searching for more benchmark circuits to stress CAD tools and device architectures. In this paper we present a new method to generate benchmark circuits by removing part of a real circuit and replacing it with a synthetic clone. This replacement or stitching process can easily introduce combinational loops if the synthetic circuit contains an input-to-output dependence that was not in the original subcircuit it is replacing. We show that this can be expressed as the graph monomorphism problem, and that a solution to that problem gives a precise stitching assignment that is cycle-free. This technique can be used to create new benchmark circuits that are identical to the original circuit except for small, local changes. The resulting semisynthetic benchmarks are ideal for testing incremental place and route tools.

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Synthetic Circuit Generation Using Clustering and Iteration

Cited by 25 publications

References 19 publications

Logic block clustering of large designs for channel-width constrained FPGAs

Logic block clustering of large designs for channel-width constrained FPGAs

Floating-Point FPGA: Architecture and Modeling

Semi Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

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