Semi Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

Abstract

FPGA architects are always searching for more benchmark circuits to stress CAD tools and device architectures. In this paper we present a new method to generate benchmark circuits by removing part of a real circuit and replacing it with a synthetic clone. This replacement or stitching process can easily introduce combinational loops if the synthetic circuit contains an input-to-output dependence that was not in the original subcircuit it is replacing. We show that this can be expressed as the graph monomorphism problem, and that a solution to that problem gives a precise stitching assignment that is cycle-free. This technique can be used to create new benchmark circuits that are identical to the original circuit except for small, local changes. The resulting semisynthetic benchmarks are ideal for testing incremental place and route tools.

Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route

“…In [6], a method of using existing synthetic circuit generators to generate R from S and also to "stitch" R into N \S was presented. It was shown that care is required in the stitching process to avoid the inadvertent creation of combinational loops in the overall circuit.…”

“…It was shown that care is required in the stitching process to avoid the inadvertent creation of combinational loops in the overall circuit. The stitching method in [6] transformed the problem into a graph matching problem which was solved using existing tools. However, the problem is combinatorially complex, and required the use of imprecise heuristics with unpredictable run times to produce a stitched solution.…”