Logic block clustering of large designs for channel-width constrained FPGAs

Abstract

In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2,3,11] aim to reduce the amount of inter-cluster connections, hence reducing channel width needs. However, if this exceeds the FPGA's channel width (a hard constraint), then the circuit still cannot be routed. Previous work [11,12] depopulates logic clusters (CLBs) to reduce channel width. By depopulating non-uniformly, i.e. depopulate more in hard-to-route regions, we show a graceful trade-off between channel width and CLB count. This makes it possible to target specific channel-width constraints during clustering with minimal CLB inflation. Results show channel width decreases of up to 20% with a 5% increase in area. Further decreases of nearly 50% are possible at 3.3 times the original area. Despite the area increase, this technique creates routable solutions from otherwise-unroutable circuits.

Improving Timing-Driven FPGA Packing with Physical Information

“…2 Table 5 indicates that there is only a small increase in the number of clusters made by DPACK or HDPACK. It is important to note that, in our approach, the improvement seen from the use of physical information is not a manifestation of depopulated CLBs, which has been shown to help routability at the expense of area [16]. We note that DPACK and HDPACK achieve remarkably good net absorption (not to mention routed critical path delays and wire lengths, as discussed previously) given that they produce very little depopulation compared to other techniques.…”

T-NDPack: Timing-driven non-uniform depopulation based clustering

“…Therefore, nonuniform depopulation results with better routability in congested area and higher CLB utilization in un-congested area compared to uniform scheme. Tom [12] proposes the first non-uniform depopulation methodology. They use 20 MCNC benchmark circuits [13] and connect them with three different topologies.…”

“…We categorize them into two types ( Fig. 1): uniform depopulation ( [10] and [11]) and non-uniform depopulation ( [9] and [12]). Uniform depopulation sets a fixed "upper limit" per CLB and each CLB is filled to that "upper limit" capacity.…”

“…However depopulation leads to more external connec- [3] P-T-VPack, [7] T-VPack, [4] T-RPack, [5] HDPack, [6] iRac, [10] R. Tessier, [11] *T-NDPack Un/DoPack, [9] M. Tom, [12] tions among CLBs and typically results with an increase in critical path delay, because the inter-CLB delays are much larger than the intra-CLB delays [1]. For example, the latest depopulation clustering technique [9] decreases minimum channel width by 15% while increasing the number of CLBs by 17.32% compared to T-VPack [4].…”

Regular Routing Architecture for a LUT-based MPGA

“…This results in a greater number of tiles in the relaxed placement. Lemieux shows in [4] that if we depopulate tiles of logic c ells the number of tracks per channel can be reduced. The other option concerns with the MPGA routing tool.…”