Portable wireless multimedia approaches traditionally achieve the specified performance and power consumption with a hardwired accelerator implementation. Due to the increase of algorithm complexity (Shannon's law), flexibility is needed to achieve shorter development cycles. A coarse-grained reconfigurable computing concept for these requirements is discussed, which supports both flexible control decisions and repetitive numerical operations. The concept includes an architecture template and a compiler and simulator environment. The architecture provides flexible time -multiplexing of code for highperformance data processing while keeping the configuration bandwidth and power requirements low. The purpose of this study is to use the coarse-grained architecture for H.264/AVC in order to determine at the physical level whether reconfigurable computing, highperformance and low-power can be obtained.
Mask Programmable Gate Arrays (MPGAs) are an attractive solution to reduce design cost and turnaround time in ultra-deep submicron technologies. Several design methodologies have been proposed in the recent years for converting an evaluated Field-Programmable Gate-Array (FPGA) prototype design into an MPGA. In this paper, we investigate a predefined regular routing architecture of an MPGA. The routing architecture is easily scalable. A simple model for the MPGA interconnect is presented which facilitates static timing analysis. We explain the difference of this interconnect with the FPGA interconnect. The resulting MPGA is implemented in 130nm. Circuit level simulations show that our model is accurate in terms of delay. The study presents tradeoffs with the placement and routing to reach timing closure. A special MPGA routing tool is used. The study shows that high number of tracks in the MPGA is area prohibitive, but with better timing closure.
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