Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes

Abstract

Portable wireless multimedia approaches traditionally achieve the specified performance and power consumption with a hardwired accelerator implementation. Due to the increase of algorithm complexity (Shannon's law), flexibility is needed to achieve shorter development cycles. A coarse-grained reconfigurable computing concept for these requirements is discussed, which supports both flexible control decisions and repetitive numerical operations. The concept includes an architecture template and a compiler and simulator environment. The architecture provides flexible time -multiplexing of code for highperformance data processing while keeping the configuration bandwidth and power requirements low. The purpose of this study is to use the coarse-grained architecture for H.264/AVC in order to determine at the physical level whether reconfigurable computing, highperformance and low-power can be obtained.

A Survey on Dynamically Reconfigurable Processors

“…Although context switching can be done with a clock cycle in multicontext devices, the area of each PE is increased with the distributed context memory. The area of configuration memory which provides 32 contexts is almost the same as that of a PE itself [9].…”

“…Instead, the number of available contexts is strictly limited in dynamically reconfigurable processors, and it is difficult to execute complicated programs. ADRES [9] has a VLIW part in the array of PEs. As shown in Fig.…”

Multi-objective optimization and multi-criteria decision aid applied to the design of 3D-stacked integrated circuits

“…The considered MPSoC is made of 13 blocks as shown on Figure 3.7: -6 processors (CPU, based on [87]) -2 data memories (L2D#) -2 instruction memories (L2Is#) -1 external memory interface (EMIF) -1 input/output control processor (FIFO) Details about the area required for each component is given in Table 3.9 for a 90 nm technology. This table is also the input matrix required to specify the scenario.…”

A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

“…Coarse-Grained Reconfigurable processor Arrays (CGRA) [5,2,6] have received attention as energy efficient accelerators for various types of battery driven mobile devices, and some of them have been utilized in commercial products [8,7]. CMA (Cool Mega Array) [10] is a CGRA architecture especially designed focusing on energy efficiency.…”