Non-Volatile Memories for Removable Media

Micheloni, Rino; Picca, M.; Amato, Stefano; Schwalm, Helmut; Scheppler, M.; Commodaro, S.

doi:10.1109/jproc.2008.2007477

Cited by 39 publications

(11 citation statements)

References 18 publications

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“…The effective dimension of NAND devices now appears to lead the DRAM half pitch [1]. In the near future it is expected that Flash-based memory systems such as solid state drives (SSDs) will gradually replace conventional hard disc drives (HDDs) [2]. This evolution is supported by two main trends of the NAND Flash memories: increasing cell density per die (transistors narrowing) and increasing information storage (2 bit, 3 bit, etc.)…”

Section: Introductionmentioning

confidence: 99%

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Poliakov

Blomme

Corbalan

et al. 2011

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Poliakov

Blomme

Corbalan

et al. 2011

Microelectronics Reliability

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“…The SWLUpdate is as shown in algorithm 2: whenever the data block PBA is updated, copy valid data to cache and add it to invalid blocks (step 1-2). Then check the position pointers (step [3][4][5][6][7][8]. If block A is the updated one, search new block A (step 3-5).…”

Section: Methodsmentioning

confidence: 99%

Enhancing Endurance of Huge-Capacity Flash Storage Systems by Selectively Replacing Data Blocks

Wang

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYThe wear leveling is a critical factor which significantly impacts the lifetime and the performance of flash storage systems. To extend lifespan and reduce memory requirements, this paper proposed an efficient wear leveling without substantially increasing overhead and without modifying Flash Translation Layer (FTL) for huge-capacity flash storage systems, which is based on selective replacement. Experimental results show that our design levels the wear of different physical blocks with limited system overhead compared with previous algorithms.

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“…In our simulation, we assume using MLC flash and set its memory read access time as and program time as [10] for normal speed write with retention time is 10 years. We set the data retention time for fast-write as 4 days.…”

Section: An Approximate Memory Device Modelmentioning

confidence: 99%

OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite

Zhang

2014

IEEE Trans. Comput.

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This paper presents a cross-layer design strategy to reduce SSD response time and its variation. The key is to cohesively exploit system-level run-time data access workload variation and temporal locality and device-level NAND flash memory write latency versus data retention time trade-off. The basic idea is simple: once write intensity of the workload increases and begins to degrade SSD response time, we speed up memory programming at the penalty of shorter data retention time, and rewrite these short-lifetime data later, if necessary, when workload write intensity drops. A scheduling solution is developed to effectively implement this design strategy. Simulations over various workloads were carried out and the results demonstrate that the cross-layer design strategy can reduce the average SSD response time by up to 52.3%.

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Non-Volatile Memories for Removable Media

Cited by 39 publications

References 18 publications

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Enhancing Endurance of Huge-Capacity Flash Storage Systems by Selectively Replacing Data Blocks

OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite

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