Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

IEEE Trans. Signal Process.

2014

High-density NAND flash memory suffers from the data retention problem because even small charge leakage incurs a large threshold voltage shift as the transistor size shrinks. In this paper, we develop a decision directed estimation (DDE) algorithm to know the effects of charge leakage in NAND flash memory using the error pattern of the accessed data. While the conventional sensing directed estimation (SDE) method demands extra memory sensing to know the signal distribution, the proposed DDE algorithm induces no sensing overheads. The proposed algorithm approximates the threshold voltage distribution as a Gaussian mixture and also assumes that the increase of standard deviation is linearly proportional to the amount of mean shift. Since the threshold voltage distribution in real devices is not a perfect Gaussian mixture, we conduct error analysis of the proposed algorithm to examine the sources of estimation errors and quantify their impact on the estimation accuracy. We also present a combined estimation scheme that employs the DDE and the SDE algorithms to minimize the number of memory sensing operations while maintaining high estimation accuracy. The developed algorithm is applied to both simulated and real NAND flash memory, and the estimation errors are measured.

Section: A Modeling Error In the Threshold Voltage Distributionmentioning

confidence: 99%

Section: A Modeling Error In the Threshold Voltage Distributionmentioning

confidence: 99%

Section: A Decision Directed Estimation With Simulated Nand Flash Mementioning

confidence: 99%

See 1 more Smart Citation

Decision Directed Estimation of Threshold Voltage Distribution in NAND Flash Memory

Lee

IEEE Trans. Signal Process.

2014

“…The former utilizes the output signals of multi-level voltage sensing to eliminate the CCI when reading memory, while the latter modifies the target programming voltage of the ISPP (incremental step pulse programming) scheme to compensate the CCI when a writing page. Since the coupling coefficients have different values according to the locations of victim cells [17], an adaptive LMS (least mean square) filter based coupling canceller was proposed in [15]. This approach continuously updates the coefficients of the CCI canceller by using a single data sample at each iteration.…”

Section: Cell-to-cell Interference Cancellation and Soft-information mentioning

confidence: 99%

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Lee

Kim

2013

SiPS 2013 Proceedings

The capacity of NAND flash memory has been continuously increased by adopting process technology scaling and multi-level cell (MLC) data coding. However, the reliability of stored data becomes a very important issue because the scaled feature size lowers the number of electrons at each floating-gate while increasing the cell-to-cell interference. In this paper, we review recent advances in signal processing techniques for reliability improvement of sub-20 nm NAND flash memory, which includes estimation of the threshold voltage distribution, cell-to-cell interference cancellation, and optimal multi-level memory sensing. We also present experimental results for the explained signal processing algorithms. Especially, we demonstrate the reliability improvement when combining all these techniques.

“…The number of PE cycles and retention time vary from 1 to 5K times and from 1 to 9K hours, respectively. The coupling coefficients of the x and xy directions are set to 0.1034 and 0.006721, respectively, in order to consider 20-nm Flash memory technology [23,24]. We can find that the total energy consumption is very strongly affected by the PE cycling.…”

Section: Low-energy Error Correction Scheme For Nand Flash Memorymentioning

confidence: 99%

Low-energy error correction of NAND Flash memory through soft-decision decoding

Kim

EURASIP J. Adv. Signal Process.

2012

The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.