Low-energy error correction of NAND Flash memory through soft-decision decoding

Kim, Jonghong; Sung, Wonyong

doi:10.1186/1687-6180-2012-195

Cited by 19 publications

(11 citation statements)

References 18 publications

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“…The read operation of NAND flash memory involves address decoding, cell array accessing, and data output. According to the timing parameters in [14], the SDE with 12-level voltage sensing requires approximately per page only for the memory sensing operations. In order to apply the SDE algorithm to TLC NAND plots when the numbers of PE cycles are 3 K and 5 K times.…”

Section: B Applying To Two-bit Mlc Nand Flash Memorymentioning

confidence: 99%

Decision Directed Estimation of Threshold Voltage Distribution in NAND Flash Memory

Lee

Sung

2014

IEEE Trans. Signal Process.

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High-density NAND flash memory suffers from the data retention problem because even small charge leakage incurs a large threshold voltage shift as the transistor size shrinks. In this paper, we develop a decision directed estimation (DDE) algorithm to know the effects of charge leakage in NAND flash memory using the error pattern of the accessed data. While the conventional sensing directed estimation (SDE) method demands extra memory sensing to know the signal distribution, the proposed DDE algorithm induces no sensing overheads. The proposed algorithm approximates the threshold voltage distribution as a Gaussian mixture and also assumes that the increase of standard deviation is linearly proportional to the amount of mean shift. Since the threshold voltage distribution in real devices is not a perfect Gaussian mixture, we conduct error analysis of the proposed algorithm to examine the sources of estimation errors and quantify their impact on the estimation accuracy. We also present a combined estimation scheme that employs the DDE and the SDE algorithms to minimize the number of memory sensing operations while maintaining high estimation accuracy. The developed algorithm is applied to both simulated and real NAND flash memory, and the estimation errors are measured.

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Section: B Applying To Two-bit Mlc Nand Flash Memorymentioning

confidence: 99%

Decision Directed Estimation of Threshold Voltage Distribution in NAND Flash Memory

Lee

Sung

2014

IEEE Trans. Signal Process.

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“…We considered a maximum operating temperature of 70 • C. We calculated the RBER for different configurations running a wide range of real-life workload traces [31]. Using the RBER values, we then calculated corresponding ECC latency and energy consumption values for a 2.0 bit soft-decision LDPC scheme [19].…”

Section: Evaluation Setupmentioning

confidence: 99%

“…Unfortunately, the energy and latency overheads of such mechanism would be overwhelming, as the ECC overheads increase super-linearly with error rate. Figure 1(b) shows the latency and energy overheads for a 3D NAND system employing a low-density parity-check (LDPC) [10,19]…”

Section: Introductionmentioning

confidence: 99%

ReveNAND

Shihab¹,

Zhang

Kandemir

2018

ACM Trans. Archit. Code Optim.

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The paradigm shift from planar (two dimensional (2D)) to vertical (three-dimensional (3D)) models has placed the NAND flash technology on the verge of a design evolution that can handle the demands of next-generation storage applications. However, it also introduces challenges that may obstruct the realization of such 3D NAND flash. Specifically, we observed that the fast threshold drift (fast-drift) in a charge-trap flash-based 3D NAND cell can make it lose a critical fraction of the stored charge relatively soon after programming and generate errors. In this work, we first present an elastic read reference (V Ref) scheme (ERR) for reducing such errors in ReveNAND-our fast-drift aware 3D NAND design. To address the inherent limitation of the adaptive V Ref , we introduce a new intra-block page organization (hitch-hike) that can enable stronger error correction for the error-prone pages. In addition, we propose a novel reinforcement-learning-based smart data refill scheme (iRefill) to counter the impact of fast-drift with minimum performance and hardware overhead. Finally, we present the first analytic model to characterize fast-drift and evaluate its system-level impact. Our results show that, compared to conventional 3D NAND design, our ReveNAND can reduce fast-drift errors by 87%, on average, and can lower the ECC latency and energy overheads by 13× and 10×, respectively.

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“…In particular, the postcompensation detector [1] and the coupling canceller detector [2] subtract estimates of ICI from the noisy observations of the channel output (i.e., the sensed voltage of each cell). Some "soft" detection strategies were also presented by using uniform and/or non-uniform channel output quantizations and then introducing the soft (decision) information in [3][4][5]. To the best of our knowledge, there exists no open literature providing an exact soft-output detector without channel output quantization in MLC flash memories.…”

Section: Introductionmentioning

confidence: 99%

All-bit-line MLC flash memories: Optimal detection strategies

Huang

Asadi

Kavcic

et al. 2014

2014 IEEE International Conference on Communications (ICC)

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We are concerned with the optimal detector design for the all-bit-line MLC flash memory. We provide a channel model of the MLC flash memory, where the channel parameters are mathematically tractable. Then we present an optimal maximum a-posteriori sequence detector. The optimal detector can be executed over a trellis whose branch metrics can be computed by using Fourier transforms of analytically computable characteristic functions (corresponding to likelihood functions). The softoutput detectors for both simple one-dimensional channel models and more realistic page-orientated two-dimensional channel models are derived. Simulation results show not only that the soft-output detector has the same hard-output bit-error-rate performance as some previously known detectors did, but that the soft-output detector outperforms previously known detectors by a gain of 0.23 dB.

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Low-energy error correction of NAND Flash memory through soft-decision decoding

Cited by 19 publications

References 18 publications

Decision Directed Estimation of Threshold Voltage Distribution in NAND Flash Memory

Decision Directed Estimation of Threshold Voltage Distribution in NAND Flash Memory

ReveNAND

All-bit-line MLC flash memories: Optimal detection strategies

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