Improving Timing-Driven FPGA Packing with Physical Information

Chen, D.T.; Vorwerk, Kristofer; Kennings, Andrew

doi:10.1109/fpl.2007.4380635

Cited by 34 publications

(21 citation statements)

References 18 publications

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“…Up to this point, the algorithm description is about the same as many other greedy FPGA packers [12] [3] [4]. The part that distinguishes this packer, the part that enables architecture adaptiveness, is in the stage where the algorithm determines which primitive, if any, a candidate netlist atom should map to within a logic block.…”

Section: Interconnect-aware Packingmentioning

confidence: 94%

Towards interconnect-adaptive packing for FPGAs

Luu

Rose

Anderson

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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In order to investigate new FPGA logic blocks, FPGA architects have traditionally needed to customize CAD tools to make use of the new features and characteristics of those blocks. The software development effort necessary to create such CAD tools can be a time-consuming process that can significantly limit the number and variety of architectures explored. Thus, architects want flexible CAD tools that can, with few or no software modifications, explore a diverse space. Existing flexible CAD tools suffer from impractically long runtimes and/or fail to efficiently make use of the important new features of the logic blocks being investigated. This work is a step towards addressing these concerns by enhancing the packing stage of the open-source VTR CAD flow [17] to efficiently deal with common interconnect structures that are used to create many kinds of useful novel blocks. These structures include crossbars, carry chains, dedicated signals, and others. To accomplish this, we employ three techniques in this work: speculative packing, pre-packing, and interconnect-aware pin counting. We show that these techniques, along with three minor modifications, result in improvements to runtime and quality of results across a spectrum of architectures, while simultaneously expanding the scope of architectures that can be explored. Compared with VTR 1.0 [17], we show an average 12-fold speedup in packing for fracturable LUT architectures with 20% lower minimum channel width and 6% lower critical path delay. We obtain a 6 to 7-fold speedup for architectures with non-fracturable LUTs and architectures with depopulated crossbars. In addition, we demonstrate packing support for logic blocks with carry chains.

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Section: Interconnect-aware Packingmentioning

confidence: 94%

Towards interconnect-adaptive packing for FPGAs

Luu

Rose

Anderson

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…Power-driven Timing-driven Routability-driven P-T-VPack, [18] SMAC, [12] SCPlace, [10] T-VPack, [4] T-RPack, [9] HDPack, [13] Marrakchi et al [11] * Target less than max logic utilization: "depopulated" CLBs Uniform depopulation * Non-uniform depopulation * T-NDPack Un/DoPack, [3] Tom and Lemieux [7] iRac, [5] Tessier and Giza [6] Figure 1: Categorization of clustering techniques based on logic utilization approach and optimization goals.…”

Section: Clustering Techniquesmentioning

confidence: 99%

“…Therefore if few available BLEs are left in a CLB and related block is not available, it is wiser to leave the BLEs unused. Typically, clustering techniques modify the cost function ( [4,5,9]) or the algorithm flow [10] or both ( [11][12][13]). Here we summarize in what capacity the well-known approaches enhance the clustering flow and highlight where our approach stands relative to them.…”

Section: Unrelated Block Clusteringmentioning

confidence: 99%

“…The latest clustering technique, HDPack [13], uses a global placer to determine approximate BLE locations. Then the algorithm uses this placement information (physical information) in the clustering cost function.…”

Section: Unrelated Block Clusteringmentioning

confidence: 99%

“…End if (11) If the related blocks available (12) Choose a related block with highest gain from the candidate block list (13) Else if (current utilization level < "unrelated block threshold" (UBT)) (14) Choose a unrelated block with the highest gain from the candidate block list //unrelated block Clustering (15 (c) Next, we categorize the blocks in the candidate block list into related and unrelated blocks: a block is related if it shares inputs or outputs with the current CLB under consideration.…”

mentioning

confidence: 99%

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Timing-Driven Nonuniform Depopulation-Based Clustering

Liu

Akoglu

2010

International Journal of Reconfigurable Computing

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Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the lowcost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulationbased clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

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