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Abstract-This paper describes a new kind of detailed routing algorithm that has been designed specifically for field-programmable gate arrays (FPGA's). The algorithm is unique in that it approaches this problem in a general way, allowing it to be used over a wide range of different FPGA routing architeetures. The detailed routing of FPGA's is a new problem and can be more difficult than classic detailed routing because the wiring segments that are available for routing are Preplaced and can only be ~onnected together in specified patterns. In some FPGA's, the routing architecture places exacting limitations on the routing choices for any connection, and in such cases there will routing channels in the FPGA where overlapping routing alternatives of two or more connections create figure, scare routing resources by considering the side effects that the routing of one connection has on another, and also has the abila routing switch is shown as an x, a wiring segment as a dotted line. and a Dossible route as a solid line. Now.ity to optimize the routing delays Of time-critical connections.CGE has been used to obtain excellent routing results for severa1 industrial circuits implemented in FPGA's with various routine. architectures. The results show that CGE is able to assume that a router first completes connection A. If the wiring segment numbered is chosen for A, then one of connections and cannot be routed because they both route ielatively large FPGA's in very close to the minimum number of tracks as determined by global routing, and it can SUCCeSSfUlly Optimize the routing delays Of time-critical connections. CGE has a linear run time over circuit size.rely on the same single remaining option, namely the wiring segment numbered 1. The correct solution is for the router to choose the wiring segment numbered 2 for connection A, in which case both B and C are also routable. Although this is a simple example, it illustrates the essence of the problems that occur because of limited rout-
In this paper, an iterative technology mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge delay model, as opposed to the more common unit delay model, is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution and the second heuristic bounds the depth of the mapping solution at each node. In depth-oriented mode, when targeting 5-LUTs, IMap obtains depth optimal solutions that are 13.3% and 12.5% smaller than those produced by CutMAP and FlowMAP-r0, respectively. Targetting the same LUT size in area-oriented mode, IMap obtains solutions that are 13.7% smaller than those produced by duplication-free mapping.
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