Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Manohararajah, Valavan; Brown, Stephen D.; Vranesic, Z.G.

doi:10.1109/tcad.2006.882119

Cited by 83 publications

(62 citation statements)

References 26 publications

(22 reference statements)

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“…The benchmarks used are 20 large public benchmarks from the MCNC and ISCAS'89 suites found in previous work on FPGA mapping [22][11] [29] 7 . Table 1 shows four experimental runs.…”

Section: Resultsmentioning

confidence: 99%

Boolean factoring and decomposition of logic networks

Mishchenko

Brayton

Chatterjee

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut-based view of a logic network, 2) exploiting the uniqueness and speed of disjoint-support decompositions, 3) a new heuristic for speeding these up, 4) extending these to general decompositions, and 5) limiting local transformations to functions with 16 or less inputs so that fast truth table manipulations can be used in all operations. Boolean methods lessen the structural bias of algebraic methods, while still allowing for high speed and multiple iterations. Experimental results on K-LUT networks show an average additional reduction of 5.4% in LUT count, while preserving delay, compared to heavily optimized versions of the same networks.

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“…The benchmarks used are 20 large public benchmarks from the MCNC and ISCAS'89 suites found in previous work on FPGA mapping [22][11] [29] 7 . Table 1 shows four experimental runs.…”

Section: Resultsmentioning

confidence: 99%

Boolean factoring and decomposition of logic networks

Mishchenko

Brayton

Chatterjee

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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“…Illegal cuts were discarded during the cut generation phase. ABC also provides area-reducing post-mapping routines based on the area-flow concept [13], which we customized to target the new architectures.…”

Section: +4-lut [mentioning

confidence: 99%

Area-efficient FPGA logic elements: Architecture and synthesis

Anderson

Wang

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Abstract-We consider architecture and synthesis techniques for FPGA logic elements (function generators) and show that the LUT-based logic elements in modern commercial FPGAs are overengineered. Circuits mapped into traditional LUT-based logic elements have speeds that can be achieved by alternative logic elements that consume considerably less silicon area. We introduce the concept of a trimming input to a logic function, which is an input to a K-variable function about which Shannon decomposition produces a cofactor having fewer than K − 1 variables. We show that trimming inputs occur frequently in circuits and we propose low-cost asymmetric FPGA logic element architectures that leverage the trimming input concept, as well as some other properties of a circuit's AND-inverter graph (AIG) functional representation. We describe synthesis techniques for the proposed architectures that combine a standard cut-based FPGA technology mapping algorithm with two straightforward procedures: 1) Shannon decomposition, and 2) finding non-inverting paths in the circuit's AIG. The proposed architectures exhibit improved logic density versus traditional LUT-based architectures with minimal impact on circuit speed.

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“…It is worth reinforcing that recent work has shown that mapping quality is not compromised by using AIGs compared with other network representations [12]. The baseline mapper was executed in depth mode, which achieves the minimum depth mapping and then performs area-driven post-passes based on the area-flow concept [15]. We use 20 large combinational and sequential circuits commonly used in academic research.…”

Section: Experimental Studymentioning

confidence: 99%

Improving logic density through synthesis-inspired architecture

Anderson

Wang

2009

2009 International Conference on Field Programmable Logic and Applications

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We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's AND-inverter graph (AIG) and show their utility in mapping into the proposed logic element. Results show that while circuits mapped to a traditional 5-LUT architecture need 14% more LUTs and have 12% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 2.5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

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Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Cited by 83 publications

References 26 publications

Boolean factoring and decomposition of logic networks

Boolean factoring and decomposition of logic networks

Area-efficient FPGA logic elements: Architecture and synthesis

Improving logic density through synthesis-inspired architecture

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