Flexibility measurement of domain-specific reconfigurable hardware

Compton, Katherine; Hauck, Scott

doi:10.1145/968280.968303

Cited by 9 publications

(12 citation statements)

References 7 publications

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“…Then the area results of the algorithms are compared to each other as well as to other implementations of the input circuits. Finally, we compare the flexibility of the generated algorithms using a novel flexibility measurement technique [22].…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, this algorithm does not restrict the offsets of the created tracks as the next two algorithms do. While this can negatively impact the architecture's flexibility to implement netlists beyond the input netlist set [11], [22], the goal of the algorithm is to customize the routing architecture significantly for the given applications within the limitations of the previously described architectural style. The pseudocode for this algorithm is shown in Fig.…”

Section: B Routing Generationmentioning

confidence: 99%

“…To this end, existing circuit generation techniques [29], [30] have been modified for the heterogeneity, coarse granularity, and structure of RaPiD netlists. The synthetic RaPiD netlists can then be used to provide a greater sample set of netlists from the domain for flexibility testing [22]. This section presents the results of flexibility tests of the architecture generation algorithms using this technique.…”

Section: Flexibility Analysismentioning

confidence: 99%

“…We present a number of different tactics to generate these hardware designs, then test both the area-efficiency and flexibility of the generated architectures to verify the benefit of domain-specific hardware. This paper combines and augments two previously published works [10], [22], putting them into context with one another and presenting additional result data.…”

Section: Introductionmentioning

confidence: 97%

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Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Compton

Hauck

2008

IEEE Trans. VLSI Syst.

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Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5 smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.

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Section: Resultsmentioning

confidence: 99%

Section: B Routing Generationmentioning

confidence: 99%

Section: Flexibility Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

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Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Compton

Hauck

2008

IEEE Trans. VLSI Syst.

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“…Compton and Hauck have defined a testing method and quantification metric for flexibility of reconfigurable hardware [4]. Other examples of relevant research in reconfigurable hardware include Kim et al [8] and Chiou et al [2].…”

Section: Related Workmentioning

confidence: 99%

Applications of Small-Scale Reconfigurability to Graphics Processors

Dale¹,

Sheaffer²,

Kumar

et al. 2006

Reconfigurable Computing: Architectures and Applications

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We explore the application of Small-Scale Reconfigurability (SSR) to graphics hardware. SSR is a relatively new architectural technique wherein functionality common to multiple subunits is reused rather than replicated, yielding high-performance reconfigurable hardware with reduced area requirements. We show that SSR can be used effectively in programmable graphics architectures to allow double-precision computation without affecting the performance of single-precision calculations and to increase fragment shader performance with a minimal impact on chip area.

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A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

Theodoridis¹,

Soudris²,

Vassiliadis³

Fine- And Coarse-Grain Reconfigurable Computing

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According to the granularity of configuration, reconfigurable systems are classified in two categories, which are the fine-and coarse-grain ones. The purpose of this chapter is to study the features of coarse-grain reconfigurable systems, to examine their advantages and disadvantages, to discuss critical design issues that must be addressed during their development, and to present representative coarsegrain reconfigurable systems that have been proposed in the literature.Current and future applications are characterized by different features and demands, which increase the complexity of developing systems to implement them. The majority of contemporary applications, for instance DSP or multimedia ones, are characterized by the existence of computationally-intensive algorithms. Also, high speed and throughput are frequently needed since real-time applications (e.g. video conferencing) are widely-supported by modern systems. Moreover, due to the wide spread of portable devices (e.g. laptops, mobile phones), low-power consumption becomes an emergency need. In addition, electronic systems, for instance, consumer electronics may have strict size constraints, which make the silicon area a critical Controller CGRU CGRU CGRU CGRU CGRU CGRU Programmable Interconnections Config. Mem.

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Flexibility measurement of domain-specific reconfigurable hardware

Cited by 9 publications

References 7 publications

Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Applications of Small-Scale Reconfigurability to Graphics Processors

A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

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