Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Abstract

Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5 smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.

A Compression Algorithm Design and Simulation for Processing Large Volumes of Data from Wireless Sensor Networks

“…Furthermore, paper [11] shows how a data compression application such as collection tree protocol (CTP) is used for data collection from different sensor nodes into the root node and achieve data compression using compression algorithm in order to increase the network lifetime. Similarly, paper [12] presents a way to design/customize a reconfigurable hardware to the target application domain and make the SoC custom-fabricated. While [13] presents the generic IoT device design flow and various platform choices for IoT devices to efficiently tradeoff cost, power, performance and volume constraints.…”

Reconfigurable Computing Architectures

“…The Totem design showed how to optimize a reconfigurable array for a specific domain and illustrated the area savings in the DSP domain [65], how to perform function allocation for a domain-customized architecture [66], how to provide spare capacity for later changes [67], how to automate the layout of domain-optimized reconfigurable arrays, and how to compile applications to a specialized instance of the architecture.…”

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

“…We used Synopsys Design Compiler [11] to synthesize the examined units and the TSMC 130, 90, and 65 nm standard cell libraries. 5 We synthesized each unit with the highest optimization degree at its critical clock period and 20 higher ones with a step interval of 0.10 ns. Fig.…”

“…Existing works on coarse-grained reconfigurable datapaths mainly exploit architecture-level optimizations, e.g., increased instruction-level parallelism (ILP) [2]- [5], [7]. The domain-specific architecture generation algorithms of [5] and [9] vary the type and number of computation units achieving a customized design structure. In [2] and [4], flexible architectures were proposed exploiting ILP and operation chaining.…”