Strain relaxation in patterned strained silicon directly on insulator structures

Abstract

Strain relaxation is studied in strained silicon directly on insulator (SSDOI) substrates patterned with nanoscale features. Using interference lithography, biaxially strained SSDOI substrates with 30nm thick strained Si on insulator films were patterned into grating structures with 90nm wide stripes, and arrays of 80nm×170nm pillars. The strain profiles of these patterned structures were examined by ultraviolet Raman spectroscopy. Raman analysis of the SSDOI gratings indicates strain relaxation in the 90nm wide stripes, compared to the strain measured in unpatterned portions of the SSDOI wafer. Three-dimensional finite-element modeling of the stress distributions in the grading structures predicts that 95% of the strain is maintained in the direction along the length of the stripes. These simulations are used to decouple the strain components along the width and length of the SSDOI grating structure, inferred from Raman measurements. The results are consistent with substantial stress relaxation across the width of the stripes and very little stress relaxation along the length of the stripes.

Supercritical strained silicon on insulator

“…MOSFET active area isolation, may lead to loss of a significant fraction of strain by elastic relaxation [25]. Due to both of these considerations, it will likely be desirable to achieve as high a strain level as possible in future SSOI wafers.…”

In-depth electrical characterization of sub-45nm fully depleted strained SOI MOSFETs with TiN/HfO2 gate stack

“…process induced strain) [2]. Thus, global strain using strained FD-SOI becomes a relevant alternative for any mobility improvement as well as better short channel effects (SCE) and narrow channel effects (NCE) control [3][4][5][6][7]. Previous studies showed that the global strain tends to relax in narrow sSOI lines [4,6,7].…”

“…Thus, global strain using strained FD-SOI becomes a relevant alternative for any mobility improvement as well as better short channel effects (SCE) and narrow channel effects (NCE) control [3][4][5][6][7]. Previous studies showed that the global strain tends to relax in narrow sSOI lines [4,6,7]. In this work, FD-sSOI CMOS transistors [8], with very aggressive dimensions for both gate length and width and also for two different devices orientations, are analysed in details and they showed excellent electrical performances.…”

Anisotropy of strain relaxation in (100) and (110) Si/SiGe heterostructures

“…[37][38][39] The model suggests that the symmetry of the (001) relaxation can be reduced by patterning the SiGe layer into (sub) micrometer narrow 110 ½ stripes. The average path length of TDs moving in the 110 ½ direction is shortened by the two stripe boundaries, resulting in a reduction of the MD density in this direction and, correspondingly to a reduction of the degree of relaxation in the [110] direction.…”