2008
DOI: 10.1016/j.sse.2007.10.039
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In-depth electrical characterization of sub-45nm fully depleted strained SOI MOSFETs with TiN/HfO2 gate stack

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Cited by 7 publications
(2 citation statements)
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“…In this context, Silicon-On-Insulator (SOI) technology is increasingly used to process high performance and low power circuits. The planar SOI technology is an excellent candidate to reach specifications for future technologies [1] but their performances could be improved with innovative technological options such as: a front gate stack including a high permittivity (high-k) dielectric and a metal gate, or increased carrier mobilities due to mechanical stress induced in the active silicon area [2][3][4][5][6].…”
Section: Introductionmentioning
confidence: 99%
“…In this context, Silicon-On-Insulator (SOI) technology is increasingly used to process high performance and low power circuits. The planar SOI technology is an excellent candidate to reach specifications for future technologies [1] but their performances could be improved with innovative technological options such as: a front gate stack including a high permittivity (high-k) dielectric and a metal gate, or increased carrier mobilities due to mechanical stress induced in the active silicon area [2][3][4][5][6].…”
Section: Introductionmentioning
confidence: 99%
“…However, the strain in the sSOI channel and in turn the performance of the MOSFETs strongly depends on the device geometries and especially on the active width [6,[14][15][16][17]. This behaviour has been qualitatively studied in the case of narrow devices by Raman spectroscopy [18,19] to show the impact of the elastic strain relaxation.…”
Section: Introductionmentioning
confidence: 99%