2010
DOI: 10.1016/j.sse.2010.04.032
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Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI)

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Cited by 15 publications
(2 citation statements)
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“…This can be realized using tensile strained silicon-on-insulator substrates (SSOI), which combine strained Si and Si-on-insulator technologies and eliminate the difficulties associated with SiGe layers (high leakage current, Ge diffusion, and enhanced n-type dopant diffusion). Recently, these characteristics were demonstrated to yield higher-performance fully depleted MOSFETs compatible with the 22 nm technology node [21]. Expectedly, nanoscale patterning-a crucial step in device processing-was found to induce partial and nonuniform relaxation of the strain in SSOI-based devices [12][13][14][15][16][17][18][19].…”
Section: Introductionmentioning
confidence: 99%
“…This can be realized using tensile strained silicon-on-insulator substrates (SSOI), which combine strained Si and Si-on-insulator technologies and eliminate the difficulties associated with SiGe layers (high leakage current, Ge diffusion, and enhanced n-type dopant diffusion). Recently, these characteristics were demonstrated to yield higher-performance fully depleted MOSFETs compatible with the 22 nm technology node [21]. Expectedly, nanoscale patterning-a crucial step in device processing-was found to induce partial and nonuniform relaxation of the strain in SSOI-based devices [12][13][14][15][16][17][18][19].…”
Section: Introductionmentioning
confidence: 99%
“…4 The latest developments have led to a high-performance 14 nm-technology using Fully Depleted Silicon On Insulator (FDSOI) transistors and the integration of a strained SiGe channel in p-type MOSFETs. [5][6][7] The choice of strained SiGe as a channel was driven by two factors : firstly, hole mobility in Germanium is higher than in Silicon and secondly, heteroepitaxy of SiGe on Si yields a biaxial compressive stress in the layer, which also enhances the hole mobility of a SiGe p-MOS channel. 8 In general, the mechanical loading of the transistor channel can be performed by four basic methods by using a: (i) Contact-Etch Stop Layer (CESL), e.g.…”
Section: Introductionmentioning
confidence: 99%