Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

Khakifirooz, A.; Cheng, K.; Nagumo, T.; Loubet, N.; Adam, Thomas; Reznicek, A.; Kuss, J.; Shahrjerdi, Davood; Sreenivasan, R.; Ponoth, S.; He, Hong; Kulkarni, P.; Liu, Q.; Hashemi, Pouya; Khare, Prasanna; Luning, S.; Mehta, S.; Gimbert, J.; Zhu, Ye; Zhu, Zhengmao; Li, J.; Madan, A.; Levin, T. M.; Monsieur, F.; Yamamoto, Tetsuya; Naczas, Sebastian; Schmitz, Stefan; Holmes, Steven J.; Aulnette, C.; Daval, N.; Schwarzenbach, W.; Nguyen, Bich‐Yen; Paruchuri, Vamsi; Khare, Mukesh; Shahidi, G.; Doris, B.

doi:10.1109/vlsit.2012.6242489

Cited by 37 publications

(20 citation statements)

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“…One particular structural innovation for better gate control is the move from bulk silicon substrates to silicon-on-insulator (SOI) substrates to avoid other short channel effects such as punch through leakage current 5,6,7,8 . IBM made the first 64 bit power microprocessor in 0.22um CMOS SOI technology in 1997 9 .…”

Section: Channel and Gate Engineeringmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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Section: Channel and Gate Engineeringmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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show abstract

“…Many device structures which demonstrate better performances or scalability have been reported. Physically, even better device structures [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] have been proposed and many feasible fabrication techniques have been developed. In the FinFET or tri-gate structure, the current flows on the three surface regions and that provides even better electrostatic control.…”

Section: New Device Structuresmentioning

confidence: 99%

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Wong

Iwai

2015

Microelectronic Engineering

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“…Hence, 3-D multigate and/or ultrathin-body devices having a lightly doped channel have been adopted in industry for sub-32-nm technology node. Despite the transistor war between FinFET/tri-gate MOSFETs [23] and FD-SOI MOSFETs [24], these advanced device structures (shown in Fig. 4) can be robust to the RDF because of the lightly doped channel and better gate-to-channel capacitive coupling of the multiple gates and/or ultra-thin bodies.…”

Section: Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

Cited by 37 publications

References 0 publications

Scaling Challenges for Advanced CMOS Devices

Scaling Challenges for Advanced CMOS Devices

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Analysis of Random Variations and Variation-Robust Advanced Device Structures

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