Statistical Study for Electromigration Reliability in Dual-Damascene Cu Interconnects

Lee, Ki‐Don; Ho, Paul S.

doi:10.1109/tdmr.2004.827679

Cited by 37 publications

(15 citation statements)

References 39 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Chain structures have been used for reliability studies of BEOL wiring [15,16], and for studies of bump interconnects [8,9,17]. The "weakest link" analytical model has been used in the BEOL studies as well as studies of fine-line interconnects [18].…”

Section: Electromigration Test Methodologymentioning

confidence: 99%

Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications

Wright

Polastre

Gan³

et al.

56th Electronic Components and Technology Conference 2006

View full text Add to dashboard Cite

This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, highcurrent, high-density bump interconnections can be achieved for Si-carrier technology. IntroductionSilicon-carrier System-on-Package (SOP) technology offers much promise for a number of electronic packaging applications [1,2]. Several key technology components are required to enable this technology, including Si through-vias, high-density wiring, and high-density, controlled-collapse chip-connection (C4) interconnects between the silicon chip and silicon carrier (micro-bumps). Micro-bump flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and also enable high-performance signal and power connections. Although small C4 bumps were first fabricated in the 1960's, the packaging industry is only now moving toward bump arrays smaller than standard 100 µm diameter on 200 µm pitch (4-on-8). When combined with high-density wiring in the Sicarrier, high-density interconnections allow increased signal bandwidth between multiple chipsets, with little or no reduction in signal quality. Of equal importance, a high density array of power and ground interconnections allows improvements in power distribution design, especially for applications involving power cycling. Questions remain concerning the viability of fine-pitch bump arrays, particularly for package components with different thermal expansion coefficients (CTE). For Sn-based solders, there is strong formation of brittle intermetallic compounds (IMCs) over time. As the bump size decreases, the ratio of volume to surface area decreases, so the IMCs will constitute a larger portion of the bump.

show abstract

Section: Electromigration Test Methodologymentioning

confidence: 99%

Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications

Wright

Polastre

Gan³

et al.

56th Electronic Components and Technology Conference 2006

View full text Add to dashboard Cite

show abstract

“…In fact, the EM mechanism leading to failure in Cu is a controversial topic as many studies conducted with various testing methods have produced wide-ranging activation energies, implying that the dominant failure mechanism is highly dependent on sample configuration and the test methods. Nevertheless, in near-bamboo and bamboo structures, the activation energies for oxides, porous MSQs (methylsilsesquioxane), and organic polymer dielectrics were found to be in the range of 0.8-1.0 eV, suggesting that the mass transport is dominated by interfacial drift diffusion at the Cu and SiN x cap-layer interface regardless of the dielectric materials (Lee and Ho, 2004). Similarly, Liniger et al (2002) suggested that grain thinning or edge displacement mechanisms are responsible for the cathode void growth, and the surface drift-diffusion paths are the primary agents for the necessary mass transport, in their in situ studies on the void growth kinetics in unpassivated Cu damascene lines with TaN/Ta liner.…”

Section: Introductionmentioning

confidence: 99%

Cathode edge displacement by voiding coupled with grain boundary grooving in bamboo like metallic interconnects by surface drift-diffusion under the capillary and electromigration forces

Oǧurtani¹,

Akyıldız²

2008

International Journal of Solids and Structures

View full text Add to dashboard Cite

The kinetics of cathode edge shrinkage and displacement (drift) coupled strongly with the grain boundary (GB) grooving is investigated using the novel mathematical model developed by Ogurtani, in sandwich type thin film bamboo lines. The computer simulations are performed under the constant current (CC) and the switch-over constant voltage (SOCV) operations. The cathode drift velocity and the cathode failure time show the existence of two distinct phases, depending upon the normalized electron wind intensity parameter v; the capillary (v 6 0.01) and the electromigration (EM) dominating regimes (v > 0.01), having current exponent n, equal to 0 and 1, respectively. Analysis of various experimental data on the cathode drift velocity results a consistent value for the surface drift-diffusion coefficient, 1:0 Â 10 À5 expðÀ1:00 eV=kT Þ m 2 s À1 , for copper interconnects exposed to some contaminations during the processing and testing stages. This is found to be an excellent agreement with the experimental values reported in the literature after applying the proper 1/kT correction on the apparent activation enthalpy associated with Nernst-Einstein mobility relationship. The complete cathode failure time (CCFT) due to the cathode area shrinkage by voiding is also formulated by inverse scaling and normalization procedures, which show exactly the same capillary and EM dominating regimes. This formula can be used to predict very accurate CCFT for metallic lines with bamboo-like, near-bamboo, and even with polycrystalline structures by proper calculation of the cathode-edge path length (CEPL) parameter, in terms of the actual line width, the thickness and the grain size.

show abstract

“…The threshold product value depends on the interconnect mechanical properties and is usually determined through accelerated life tests at a temperature far above the product operating temperature. However, it is still not clear from previous works whether (jL) c is temperature dependent [2,3,4] or not [5,6,7]. An accurate temperature dependence assessment is therefore necessary in order to derive (jL) c value at operating conditions.…”

Section: Introductionmentioning

confidence: 99%

Temperature scaling of electromigration threshold product in Cu/low-K interconnects

Petitprez

Doyen

Ney

2009

2009 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

In this paper, we report on the temperature dependence of electromigration threshold product in copper interconnects. The electromigration threshold product (jL) c is first determined from lifetime distributions for temperatures ranging from 260°C to 330°C. We then propose an alternative method to determine (jL) c at much lower temperatures. We show that the threshold product does not vary significantly in the investigated temperature range. We demonstrate this alternative method is suitable to determine (jL) c close to the final product operating temperature, which would require unrealistic test duration if performed with a conventional method based on lifetime data.

show abstract

Statistical Study for Electromigration Reliability in Dual-Damascene Cu Interconnects

Cited by 37 publications

References 39 publications

Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications

Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications

Cathode edge displacement by voiding coupled with grain boundary grooving in bamboo like metallic interconnects by surface drift-diffusion under the capillary and electromigration forces

Temperature scaling of electromigration threshold product in Cu/low-K interconnects

Contact Info

Product

Resources

About