Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (,10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

In this paper we have analyzed the influence of the mask channel length (LM) on the performance of the 55-nm-hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), incorporating nitrogen-rich hydrogenated amorphous silicon nitride gate dielectric and phosphorus-doped microcrystalline silicon (n+μc-Si:H) source/drain (S/D) contacts. In our TFTs the n+μc-Si:H S/D contacts have a specific contact resistance around or below 0.5 Ω cm2. We have shown that in our TFTs a field-effect mobility and threshold voltage are dependent on LM, and this dependence is most likely due to the influence of the S/D contact series resistance on TFTs characteristics. Finally, we have demonstrated that if the mask channel length is extended by a ΔL (which is a distance from the S/D via edge at which the electron injection/collection is taking place) the field-effect mobility and threshold voltage are independent of the channel length. In such a case μFE, VT, and ON/OFF current ratio around 0.76 cm2/V s, 2.5 V, and 107, respectively, has been obtained.

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This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, highcurrent, high-density bump interconnections can be achieved for Si-carrier technology. IntroductionSilicon-carrier System-on-Package (SOP) technology offers much promise for a number of electronic packaging applications [1,2]. Several key technology components are required to enable this technology, including Si through-vias, high-density wiring, and high-density, controlled-collapse chip-connection (C4) interconnects between the silicon chip and silicon carrier (micro-bumps). Micro-bump flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and also enable high-performance signal and power connections. Although small C4 bumps were first fabricated in the 1960's, the packaging industry is only now moving toward bump arrays smaller than standard 100 µm diameter on 200 µm pitch (4-on-8). When combined with high-density wiring in the Sicarrier, high-density interconnections allow increased signal bandwidth between multiple chipsets, with little or no reduction in signal quality. Of equal importance, a high density array of power and ground interconnections allows improvements in power distribution design, especially for applications involving power cycling. Questions remain concerning the viability of fine-pitch bump arrays, particularly for package components with different thermal expansion coefficients (CTE). For Sn-based solders, there is strong formation of brittle intermetallic compounds (IMCs) over time. As the bump size decreases, the ratio of volume to surface area decreases, so the IMCs will constitute a larger portion of the bump.