Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (,10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

On-line mass spectrometry allowed the flow conditions to be quickly tuned for safe operation and optimal generation of the desired product. The validity of this approach was corroborated by off-line liquid chromatography/mass spectrometry (LC/MS) analysis of flow samples.

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Abstract-A wafer-scale, batch fabrication process for constructing quadrupole mass spectrometers using microelectromechanical systems (MEMS) technology is described. The device is formed from two bonded silicon-on-insulator ( [1447]Index Terms-Mass spectrometry, microelectromechanical systems (MEMS), quadrupole lens.

The band alignment in GaAs:(Al,Ga)As heterostructures has been investigated over the full range of alloy composition. The valence-band discontinuity ΔEv is determined by measuring the activation energy for thermionic emission of holes from p-GaAs over an undoped, square (Al,Ga)As barrier. The use of p-type structures to measure ΔEv circumvents a number of complications involved in the measurement of ΔEc. The parameters required for analysis are determined by different measurements on the same structures and the analysis is performed so that the activation energy, extrapolated to zero bias, yields ΔEv directly. It is found that ΔEv is a linear function of the aluminum mole fraction xAl: ΔEv ≂0.55xAl (eV) (0≤xAl≤1). The validity of these data is supported by measurements of ΔEc in the direct band-gap regime, where complementary values of ΔEv and ΔEc add up to the expected band-gap difference. This relationship provides a simple description of the full band alignment in this heterosystem and should prove valuable as a test of the various heterojunction lineup theories. Moreover, these measurements have a number of important consequences, particularly from the viewpoint of heterojunction devices.

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