Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

Andry, Paul; Tsang, C. K.; Webb, Bucknell C.; Sprogis, E.; Wright, S. L.; Dang, Bing; Manzer, Dennis G.

doi:10.1147/jrd.2008.5388558

Cited by 109 publications

(61 citation statements)

References 7 publications

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“…[1][2][3] The metallization of through silicon vias (TSVs), one of a promising technology for the 3D packaging, is expected to enhance the operation speed and performance of the microelectronic devices. [4][5][6][7][8] A void-free filling of the TSVs by Cu electrodeposition with proper organic additives chemistry has been actively investigated to reduce processing time.…”

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confidence: 99%

Bottom-up Filling of through Silicon Vias Using Galvanostatic Cu Electrodeposition with the Modified Organic Additives

Kim

Choe

Cho

et al. 2014

J. Electrochem. Soc.

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The chemically synthesized suppressor and leveler are added together with bis(3-sulfopropyl)disulfide (SPS) to galvanostatically fill up the trenches with the similar dimensions to those of the through silicon vias. In our previous study, the deposition of the coarse-grained Cu was indicated as a drawback of the synthesized additives, i.e., polyoxy polymer with amine terminal groups and pyridine derivatives containing additional amine groups. In this study, the modified chemistry of organic additives is used, enabling the bottom-up filling of trenches and improving the microstructure of the deposited Cu. The conversion of the functional groups from amine to hydroxyl groups in both the suppressor and leveler, and the uniform adsorption of modified suppressor improved the microstructure of the deposited Cu. The void-free trench filling is induced by the selective adsorption and accumulation of SPS at the bottom and negligible deposition on the top and side-walls of the trenches. Based on the filling mechanism, the trenches with 9 μm width and 50 μm depth are galvanostatically filled in ≤20 min. Intensive researches have been focused on the fabrication of 3-dimensional (3D) interconnection among electronic devices to achieve a high-density integration and multifunctional single device.1-3 The metallization of through silicon vias (TSVs), one of a promising technology for the 3D packaging, is expected to enhance the operation speed and performance of the microelectronic devices.4-8 A void-free filling of the TSVs by Cu electrodeposition with proper organic additives chemistry has been actively investigated to reduce processing time. 9-11A concentration gradient of suppressing agent, high at the via top while decreasing gradually toward the via bottom, typically induces a bottom-up via filling. The Cu deposit according to the filling time typically reveals a V-shaped profile reflecting the gradient of additive coverage. [12][13][14] Recently, an extreme bottom-up filling of the vias was achieved using one component of additive, suppressor, resulting in a clearly flat filling profile rather than the V-shape. 15,16 Based on the previous results, L. Yang et al. reported that the difference in the adsorption density of suppressing agents between the via top and bottom was required for a void-free bottom-up filling. 17Moreover, the accumulation of accelerator at the bottom of the via was also highlighted in understanding the filling mechanism. In the case of recessed features with submicrometer dimensions, accelerators including bis(3-sulfopropyl)disulfide (SPS) promoted copper deposition, enabling the superconformal filling in the combination with suppressors, based on a curvature-enhanced-accelerator coverage (CEAC) mechanism.18-26 However, the same additive composition or deposition method used in the CEAC model itself mostly failed in the void-free filling of the TSVs. Therefore, additional steps including the selective deactivation of the adsorbed SPS on the top of the vias were introduced to improve the filling perf...

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mentioning

confidence: 99%

Bottom-up Filling of through Silicon Vias Using Galvanostatic Cu Electrodeposition with the Modified Organic Additives

Kim

Choe

Cho

et al. 2014

J. Electrochem. Soc.

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“…For short interconnections that follow (9), it may also be possible to reduce interconnect capacitance. In particular, advanced packaging techniques such as three-dimensional integration via wafer bonding [36] or silicon carriers [37] bring chips closer together, which can eliminate transmission line effects, reduce capacitance, and decrease power as compared with traditional I/O pins and boardlevel wiring. Ultimately, continued density scaling and single-chip integration can shorten many off-chip connections.…”

Section: E Off-chip Connectionsmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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“…polymers, followed by appropriate thermal processing and removal of excess material from the surface. Extensive work has been done in the development of each of these processes, and the characterization of the resulting TSV's at a variety of dimensions and pitches [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43].…”

Section: Tsv Processesmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

Cited by 109 publications

References 7 publications

Bottom-up Filling of through Silicon Vias Using Galvanostatic Cu Electrodeposition with the Modified Organic Additives

Bottom-up Filling of through Silicon Vias Using Galvanostatic Cu Electrodeposition with the Modified Organic Additives

Practical Strategies for Power-Efficient Computing Technologies

3D integration review

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