Statistical Evaluation of Process Damage Using an Arrayed Test Pattern in a Large Number of MOSFETs

Extraction of time constants ratio over nine orders of magnitude for understanding random telegraph noise in metal–oxide–semiconductor field-effect transistors

“…Figure 2 shows the circuit diagram of array test circuit for the evaluation of numerous MOSFETs. [19][20][21][22] In this test circuit, device under test (DUT) cells are consisted of measured and row switch transistors. And the DUT cells are placed in an arrayed pattern.…”

“…Using the test circuit, we can measure both the variation of I D -V GS characteristics and RTN characteristics from a large number of MOSFETs. [19][20][21][22][23] When a particular cell shows RTN, we can specify and observe it as dynamic fluctuation of V GS in the time scale. After identifying the MOSFETs showing RTN, the I D dependence of RTN characteristics in these MOSFETs are evaluated in detail by high-speed measurements with sampling period of 1 µs by fixing the shift registers addresses.…”

“…After identifying the MOSFETs showing RTN, the I D dependence of RTN characteristics in these MOSFETs are evaluated in detail by high-speed measurements with sampling period of 1 µs by fixing the shift registers addresses. 20,23,24) Figures 4 and 5 show the measurement board and a signal flow of output signal from DUT cell to field programmable gate array (FPGA), respectively. 25) The analog output signal is amplified by the source follower amplifier in the array test circuit and the differential amplifier in the measurement board, then we obtain the 12 bit digital signals by analog-todigital converter (ADC).…”

Large-Scale Test Circuits for High-Speed and Highly Accurate Evaluation of Variability and Noise in Metal–Oxide–Semiconductor Field-Effect Transistor Electrical Characteristics

“…Figure 1 show the circuit diagrams. 32) Figure 1(a) shows a unit cell and the current source. The current source placed in each column controls I ds of the source follower transistor.…”

“…Figure 2(a) shows the I ds test circuit that can measure the I ds -V gs characteristics, V th , S-factor, and RTN of I ds . [32][33][34][35][36] Figure 2(b) shows the I Gleak test circuit. Fowler-Nordheim electron stress can be applied to all of the DUTs simultaneously, and stress-induced leakage current (SILC) of I Gleak can be measured.…”