Extraction of time constants ratio over nine orders of magnitude for understanding random telegraph noise in metal–oxide–semiconductor field-effect transistors

Tatsunori, Obara; Yonezawa, Akinori; Teramoto, Akinobu; Kuroda, Rihito; Sugawa, Shigetoshi; Ohmi, Tadahiro

doi:10.7567/jjap.53.04ec19

Cited by 13 publications

(8 citation statements)

References 30 publications

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“…Noise introduced by RTSs, random telegraph noise (RTN), is one of the most extensively investigated reliability issues in state-of-art CMOS devices [8]. First observed in 1984 [8,10], RTSs have been observed in MOSFETs [11,12,14,15], static random access memory (SRAM) [16,17], resistive random access memory (ReRAM) [18][19][20][21][22][23][24][25], and flash memory devices [26][27][28][29][30][31][32][33]. Overall, quantum mechanical effects were considered to be an obstacle for the silicon (Si) industry due to their negative impacts on the operation of CMOS circuits.…”

Section: Introductionmentioning

confidence: 99%

Single Electron Memory Effect Using Random Telegraph Signals at Room Temperature

et al. 2019

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We show a manipulation of a single electron at room temperature by controlling Random Telegraph Signals (RTSs) by voltage pulses. Our silicon nanowire triple-gate transistor exhibited RTSs when potential barriers were electrically created by two of the three gates. From the statistics of the signals, we optimized the voltage pulse such that a single electron was intentionally captured in the potential well, and the retention time of approximately 10 ms was observed in this memory operation. This study indicates that a single electron effect can be controllable in a form of RTSs at room temperature by electrically defining a potential well.

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Section: Introductionmentioning

confidence: 99%

Single Electron Memory Effect Using Random Telegraph Signals at Room Temperature

et al. 2019

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“…Two kinds of gate oxide film were formed: one with a target oxide thickness of 5.8 nm for core transistors, and one with 7.7 nm for I/O transistors, but we investigated n-channel MOSFETs (nMOSFETs) with the 5.8-nm thick SiO 2 film in this study. For some samples, channel stop ion implantation (CSII) [26][27][28] was performed just before forming the trench SiO 2 film in the STI processes. CSII was done to increase the dopant concentration at the STI edge, which effectively prevents parasitic channel from forming at the STI edge; this will be discussed later.…”

Section: Methodsmentioning

confidence: 99%

Introduction of Atomically Flattening of Si Surface to Large-Scale Integration Process Employing Shallow Trench Isolation

Goto

Kuroda

Akagawa

et al. 2015

ECS J. Solid State Sci. Technol.

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Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-μm technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate–source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved.

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“…131,072 MOSFETs (L/W = 0.22/0.28 μm) were measured, and 2575 MOSFETs with large VRMS can be extracted. Then, we selected MOSFETs with large RTN and measured them by a specific measurement mode of a sampling period of 1 μs and a long sampling time of 10 min (sampling points = 6 × 10 8 ) for the same bias condition [57,58]. Figures 13-15 show the (a) waveform, (b) time lag plot (TLP), and (c) histogram for typical three-, four-, and six-state RTN.…”

Section: Multi-state Rtnmentioning

confidence: 99%

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

Teramoto

2021

Electronics

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Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO2/Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must first understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s findings are presented.

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Extraction of time constants ratio over nine orders of magnitude for understanding random telegraph noise in metal–oxide–semiconductor field-effect transistors

Cited by 13 publications

References 30 publications

Single Electron Memory Effect Using Random Telegraph Signals at Room Temperature

Single Electron Memory Effect Using Random Telegraph Signals at Room Temperature

Introduction of Atomically Flattening of Si Surface to Large-Scale Integration Process Employing Shallow Trench Isolation

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

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