Large-Scale Test Circuits for High-Speed and Highly Accurate Evaluation of Variability and Noise in Metal–Oxide–Semiconductor Field-Effect Transistor Electrical Characteristics

Abstract

To develop a new process technology for suppressing the variability and noise in metal–oxide–semiconductor field-effect transistors (MOSFETs) for large-scale integrated circuits, accurate and rapid measurement test circuits for the evaluation of a large number of MOSFET electrical characteristics were developed. These test circuits contain current-to-voltage conversion circuits and simple scanning circuits in order to achieve rapid and accurate evaluation for a wide range of measurement currents. The test circuits were fabricated and the variabilities and noises in drain–source current, gate leakage current, and p–n junction leakage current were evaluated using a large-scale test circuit.

Extraction of time constants ratio over nine orders of magnitude for understanding random telegraph noise in metal–oxide–semiconductor field-effect transistors

“…After identifying the MOSFETs showing RTN, the I D dependence of RTN characteristics in these MOSFETs are evaluated in detail by high-speed measurements with sampling period of 1 µs by fixing the shift registers addresses. 20,23,24) Figures 4 and 5 show the measurement board and a signal flow of output signal from DUT cell to field programmable gate array (FPGA), respectively. 25) The analog output signal is amplified by the source follower amplifier in the array test circuit and the differential amplifier in the measurement board, then we obtain the 12 bit digital signals by analog-todigital converter (ADC).…”

Recovery Characteristics of Anomalous Stress-Induced Leakage Current of 5.6 nm Oxide Films

“…2,3) leakage current on the order of 10 À15 A or larger for 87,344 MOSFETs continuously for a sampling time of several tens of seconds (in this experiment 83 s). 11) When stress switches are turned on, the source/drain of DUTs are connected to the ground and the gate electrode is applied at a stress voltage, Fowler-Nordheim stress was applied to all MOSFETs simultaneously. In this experiment, constant electric field stress (+10 MV/cm-1.24 mA/cm 2 ) and constant current stresses (+1 and +10 mA/cm 2 ) were applied to MOSFETs to generate anomalous SILC.…”

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

“…The test structure is constructed using 0.22 μm, 1-poly 2-metal standard CMOS technology and includes n-MOSFETs of various gate sizes [35][36][37][38] as shown in Table 1. The The electronic circuit will be influenced by noise, such as thermal noise, quantum noise, and flicker noise.…”

“…The test structure is constructed using 0.22 µm, 1-poly 2-metal standard CMOS technology and includes n-MOSFETs of various gate sizes [35][36][37][38] as shown in Table 1. The measured MOSFETs are arrayed in 1024 rows and 1776 columns (total number of MOSFETs: 1217856) in a chip at 5 µm intervals.…”