Stateful Three-Input Logic with Memristive Switches

Siemon, Anne; Drabinski, R.; Schultis, Michael J.; Hu, Xuan; Linn, Eike; Heittmann, Arne; Waser, Rainer; Querlioz, Damien; Menzel, Stephan; Friedman, Joseph S.

doi:10.1038/s41598-019-51039-6

Cited by 47 publications

(40 citation statements)

References 49 publications

(46 reference statements)

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“…Although our adder requires numerous WRITE operations, writing to a 1T-1R array can be achieved in an energy-efficient manner due to the absence of sneak currents. Sneak currents contribute to energy leakage and constitute a portion of the energy consumed in 1S-1R based adders [44], [46], while the percentage of such energy leakage is negligible in 1T-1R arrays. Overall, the proposed adder is energy-efficient, thanks to the 1T-1R configuration.…”

Section: N-bit In-memory Parallel-prefix Addersmentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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Section: N-bit In-memory Parallel-prefix Addersmentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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“…[ 11 ] Since then, its versatile derivatives have been reported for different kinds of Boolean logic gate operation. [ 12–16 ] Combining the gate operations in sequence, a complete logic cascading is carried out using only two to three memristors, proved through a full adder demonstration. [ 10,11,13 ] Unlike in the complementary metal oxide semiconductor (CMOS) logic, where the cascading occurs through the spatially distributed gates that consist of a number of transistors, stateful logic executes it through sequential gate operations at an extremely limited number of memristors.…”

Section: Introductionmentioning

confidence: 99%

A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

Yoon

Han

Bae

2020

Adv Elect Materials

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Crossbar memory has become an attractive emerging technology in that it can serve as an efficient media for this transition leveraged with two main vectors: one is to provide better performance of the existing computer architecture and the other is to seek for in-memory computing capabilities that erect on completely new computer architectures, so-called non-Von Neumann architectures. The unprecedentedly compact and highly stackable crossbar array structure is anticipated to accomplish the former through comprising a new memory hierarchy, storage class memory (SCM) that bridges the performance gap between DRAM and NAND to facilitate data transfer across different hierarchies. [5,6] On the other hand, the high compatibility of its cell element, memristor, with exotic materials brings about various forms of digital and analog switching, which provide opportunities for various in-memory computing methods ranging from Boolean logic to neuromorphic computing. [7-9] Among the new computing methods being proposed, stateful logic is one way to implement the Boolean logic within the crossbar array. [10] The name originates from the fact that the outcome of a gate operation is concurrently stored at the same spot as where the calculation is taken place, that is, the array serve as both of gates and latches. The data are stored in a non-volatile manner that in fact the crossbar memory by itself can work as a processor, memory, and storage. This implies the power and latency required for transferring data across different hierarchies, namely von Neumann bottleneck, is effectively alleviated. Borghetti et al. has first demonstrated a stateful implication logic based on a conditional writing according to a certain array operation scheme applied on two adjacent memristor cells, where on/off state of one memristor toggles depending on the resistance state of the other. [11] Since then, its versatile derivatives have been reported for different kinds of Boolean logic gate operation. [12-16] Combining the gate operations in sequence, a complete logic cascading is carried out using only two to three memristors, proved through a full adder demonstration. [10,11,13] Unlike in the complementary metal oxide semiconductor (CMOS) logic, where the cascading occurs through the spatially distributed gates that consist of a number of transistors, stateful logic executes it through sequential gate operations at an extremely limited number of memristors. Besides such arithmetic logic cascading, one useful logic operation widely adopted in the non-volatile memory (NVM)

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“…[10][11][12][13] Recent studies have identified various useful and efficient stateful gates for better computing efficiency, and as a result, stateful logic technology has advanced significantly. [14][15][16][17][18][19][20][21][22][23][24] Such various gates are possible by simultaneously applying designed operating voltages on the multiple cells. In general, the word lines of input cells and output cells are biased to a conditioning voltage (V COND ) and programming voltages (V PGM ), respectively.…”

Section: Introductionmentioning

confidence: 99%

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Kim

Song

et al. 2020

Advanced Intelligent Systems

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Memristive stateful logic allows complete in‐memory computing and is considered to be a next‐generation computing technology for low power edge applications. Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near‐memory error correction method for a typical bipolar‐type memristor stateful logic system is proposed. An error correction principles using a HfO2‐based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one‐bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.

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Stateful Three-Input Logic with Memristive Switches

Cited by 47 publications

References 49 publications

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

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