A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

Abstract

Crossbar memory has become an attractive emerging technology in that it can serve as an efficient media for this transition leveraged with two main vectors: one is to provide better performance of the existing computer architecture and the other is to seek for in-memory computing capabilities that erect on completely new computer architectures, so-called non-Von Neumann architectures. The unprecedentedly compact and highly stackable crossbar array structure is anticipated to accomplish the former through comprising a new memory hierarchy, storage class memory (SCM) that bridges the performance gap between DRAM and NAND to facilitate data transfer across different hierarchies. [5,6] On the other hand, the high compatibility of its cell element, memristor, with exotic materials brings about various forms of digital and analog switching, which provide opportunities for various in-memory computing methods ranging from Boolean logic to neuromorphic computing. [7-9] Among the new computing methods being proposed, stateful logic is one way to implement the Boolean logic within the crossbar array. [10] The name originates from the fact that the outcome of a gate operation is concurrently stored at the same spot as where the calculation is taken place, that is, the array serve as both of gates and latches. The data are stored in a non-volatile manner that in fact the crossbar memory by itself can work as a processor, memory, and storage. This implies the power and latency required for transferring data across different hierarchies, namely von Neumann bottleneck, is effectively alleviated. Borghetti et al. has first demonstrated a stateful implication logic based on a conditional writing according to a certain array operation scheme applied on two adjacent memristor cells, where on/off state of one memristor toggles depending on the resistance state of the other. [11] Since then, its versatile derivatives have been reported for different kinds of Boolean logic gate operation. [12-16] Combining the gate operations in sequence, a complete logic cascading is carried out using only two to three memristors, proved through a full adder demonstration. [10,11,13] Unlike in the complementary metal oxide semiconductor (CMOS) logic, where the cascading occurs through the spatially distributed gates that consist of a number of transistors, stateful logic executes it through sequential gate operations at an extremely limited number of memristors. Besides such arithmetic logic cascading, one useful logic operation widely adopted in the non-volatile memory (NVM)

In‐Memory Stateful Logic Computing Using Memristors: Gate, Calculation, and Application

“…The other novel stateful logic gate with a function of “Parity” has been achieved by one of the authors in the circuit structure shown in Figure 6b of “Parallelly connected special memristors + a series Resistance”. [ 63 ] A complementary resistive switching memristor was used to trigger the parity operation, which may limit the high flexibility in logic cascading. Nonetheless, the current‐driven scheme has a crucial significance to address the compromise on circuit complexity and facilitate delivering the biases on‐demand in the designing of operating conditions in the stateful logic gate.…”

“…Figure shows a survey of the reported circuits for experimental demonstrations and conceptual ideas of the proposed stateful logic gates in the past decade. [ 28,48–76 ] Nearly all the two‐input logic functions have been achieved in the stateful logic gates. Several complete logic functions, such as IMP, FALSE, NOR, and NAND, are verified by both theoretical derivation (simulation) and actual experiments, which is a feasible foundation for the implementation of complex gate operations.…”

“…For example, Yoon et al proposed a current‐driven scheme to facilitate delivering the biases on‐demand in the designing of operating conditions in the state logic gate. [ 63 ] In et al proposed a universal error correction method for checking and correcting the logic operation result by a peripheral CMOS circuit. [ 87 ] Nonetheless, the loss of circuit efficiency by the addition of these additional CMOS circuits should be carefully balanced by the gains achieved from them.…”

“…d) A conceptual diagram of Hamming ECC using even parity bits. a-c) Reproduced with permission [63]. Copyright 2021, Wiley-VCH.…”

Today’s computing challenges: opportunities for computer hardware design

“…Also, circuit designers can propose variation-tolerant or variation-compensated techniques to address the variation issue ( Athmanathan et al, 2016 ; Park et al, 2017 ; Hwang et al, 2010 ; Bae et al, 2018 ), or sneak-current cancellation scheme for the sneak current issue ( Vontobel et al, 2009 ; Shevgoor et al, 2015 ; Bae et al, 2016 ). In addition, looking further forward, RRAM is regarded to be a promising candidate for in-memory computing or neuromorphic computing, because of its capability to store analog weights ( Alibart, Zamanidoost & Strukov, 2013 ; Prezioso et al, 2015 ; Yoo, 2019 ; Xue et al, 2019 ; Kim & Williams, 2019 ; Yoon, Han & Bae, 2020 ; Wang et al, 2019 ). These approaches are believed to overcome the limitation of the current computer architecture, where we need tons of inter-disciplinary research opportunity to realize them.…”