The intrinsic stochasticity of the memristor can be used to generate true random numbers, essential for non-decryptable hardware-based security devices. Here, we propose a novel and advanced method to generate true random numbers utilizing the stochastic oscillation behavior of a NbOx mott memristor, exhibiting self-clocking, fast and variation tolerant characteristics. The random number generation rate of the device can be at least 40 kb s−1, which is the fastest record compared with previous volatile memristor-based TRNG devices. Also, its dimensionless operating principle provides high tolerance against both ambient temperature variation and device-to-device variation, enabling robust security hardware applicable in harsh environments.

The thin-film growth conditions in a plasma-enhanced atomic layer deposition for the (3.0–4.5) nm thick HfO2 film were optimized to use the film as the resistive switching element in a neuromorphic circuit. The film was intended to be used as a feasible synapse with analog-type conductance-tuning capability. The 4.5 nm thick HfO2 films on both conventional TiN and a new RuO2 bottom electrode required the electroforming process for them to operate as a feasible resistive switching memory, which was the primary source of the undesirable characteristics as the synapse. Therefore, electroforming-free performance was necessary, which could be accomplished by thinning the HfO2 film down to 3.0 nm. However, the device with only the RuO2 bottom electrode offered the desired functionality without involving too high leakage or shorting problems, which are due to the recovery of the stoichiometric composition of the HfO2 near the RuO2 layer. In conjunction with the Ta top electrode, which provided the necessary oxygen vacancies to the HfO2 layer, and the high functionality of the RuO2 as the scavenger of excessive incorporated oxygen vacancies, which appeared to be inevitable during the repeated switching operation, the Ta/3.0 nm HfO2/RuO2 provided a highly useful synaptic device component in the neuromorphic hardware system.

A memristive crossbar array (MCA) is an ideal platform for emerging memory and neuromorphic hardware due to its high bitwise density capability. A charge trap memristor (CTM) is an attractive candidate for the memristor cell of the MCA, because the embodied rectifying characteristic frees it from the sneak current issue. Although the potential of the CTM devices has been suggested, their practical viability needs to be further proved. Here, a Pt/Ta 2 O 5 /Nb 2 O 5‐ x /Al 2 O 3‐ y /Ti CTM stack exhibiting high retention and array‐level uniformity is proposed, allowing a highly reliable selector‐less MCA. It shows high self‐rectifying and nonlinear current‐voltage characteristics below 1 µA of programming current with a continuous analog switching behavior. Also, its retention is longer than 10 5 s at 150 °C, suggesting the device is highly stable for non‐volatile analog applications. A plausible band diagram model is proposed based on the electronic spectroscopy results and conduction mechanism analysis. The self‐rectifying and nonlinear characteristics allow reducing the on‐chip training energy consumption by 71% for the MNIST dataset training task with an optimized programming scheme.

Memristive stateful logic enables energy‐ and cost‐efficient in‐memory computing, which is desirable for edge computing in the coming Internet of Things  (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system‐level in‐memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1‐transistor−1‐memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look‐ahead adder. Then, an in‐memory computing layout that can perform all of the computing functions—data storing, transferring, and executing—inside the memory, addressing data traffic issues, is suggested. Finally, a software/hardware mixed stateful logic emulator that can virtually mimic array‐level in‐memory computing hardware based on cell‐level memristive characteristics is demonstrated.

Self-limited switching is a technique that can control the memristor resistance up to a specific value by limiting excessive switching. [14,15] For example, in self-limited "set" switching, a series resistor (R S ) is connected to a memristor (M). The R S -M configuration is biased with a programming voltage (V P ) to switch the M from the HRS to the LRS. Before the switching happens, if the node voltage on M is V M , the V M is almost equal to the V P because the R HRS is much larger than the resistance of R S (V M ≈ V P ). As soon as the resistance state of M changes to the lower value (i.e., the set switching happens), the LRS is not uniform because of the stochastic characteristic of the memristor switching. Afterward, the V P is redistributed by the voltage divider effect, and the redistributed V M (V M ′) is lower than the V P . Then, the V M ′ leads to additional minor set switching of the M.Here, the amount of additional set switching depends on the V M ′; if the R LRS is relatively small, the V M ′ is also small, so there is less additional set switching. However, if the R LRS is relatively high, the V M ′ is also high and this leads to additional set switching. Therefore, if enough time is allowed, the set switching can spontaneously saturate to a certain value.Self-limited "reset" switching is complicated, but it is also possible to realize by adopting both series and parallel resistor components. [14,16] If such self-limited switching is applied to control the intermediate states, more uniform intermediate states can be achieved. Furthermore, if the resistance of the intermediate states is the same as the series resistor value, one can directly copy any resistance values from the R to the M under the self-limited switching regime. This suggests that the analog data programming will be more efficient and faster.In this study, we propose a novel analog data programming method that transfers reference analog resistance values to a target memristor directly via a stateful in-memory logic operation. We demonstrate the methodology by adopting an ideal memristor model design. The desired memristive behavior, characterized by a gradual set switching without a sudden current jump, was achieved using a Ti-doped NbO x charge trap memristor, but with some discrepancy in switching behavior compared to the theoretic ideal. [17] Afterward, we introduced parallel resistors in the programming circuit to reduce the discrepancy and bring the memristor behavior closer to that of the ideal model. Finally, a computational simulation was employed Analog memristors enable compact neuromorphic computing with low power consumption. One of the issues with the technology is slow precise analog data programming. In this study, a novel analog data programming method utilizing a self-limited set switching is proposed. The method can transfer any resistance values from reference resistors to the target memristor accurately inside a crossbar array by performing an appropriate voltage clocking. An ideal memristor model based on the me...

Valence change-type resistance switching behaviors in oxides can be understood by well-established physical models describing the field-driven oxygen vacancy distribution change. In those models, electroformed residual oxygen vacancy filaments are crucial as they work as an electric field concentrator and limit the oxygen vacancy movement along the vertical direction. Therefore, their movement outward by diffusion is negligible. However, this situation may not be applicable in the electroforming-free system, where the field-driven movement is less prominent, and the isotropic oxygen vacancy diffusion by concentration gradient is more significant, which has not been given much consideration in the conventional model. Here, we propose a modified physical model that considers the change in the oxygen vacancies’ charged state depending on their concentrations and the resulting change in diffusivity during switching to interpret the electroforming-free device behaviors. The model suggests formation of an hourglass-shaped filament constituting a lower concentration of oxygen vacancies due to the fluid oxygen diffusion in the thin oxide. Consequently, the proposed model can explain the electroforming-free device behaviors, including the retention failure mechanism, and suggest an optimized filament configuration for improved retention characteristics. The proposed model can plausibly explain both the electroformed and the electroforming-free devices. Therefore, it can be a standard model for valence change memristors.

A memristive stateful neural network allowing complete Boolean in-memory computing attracts high interest in future electronics. Various Boolean logic gates and functions demonstrated so far confirm their practical potential as an emerging computing device. However, spatio-temporal efficiency of the stateful logic is still too limited to replace conventional computing technologies. This study proposes a ternary-state memristor device (simply a ternary memristor) for application to ternary stateful logic. The ternary-state implementable memristor device is developed with bilayered tantalum oxide by precisely controlling the oxygen content in each oxide layer. The device can operate 157 ternary logic gates in one operational clock, which allows an experimental demonstration of a functionally complete three-valued Łukasiewicz logic system. An optimized logic cascading strategy with possible ternary gates is ≈20% more efficient than conventional binary stateful logic, suggesting it can be beneficial for higher performance in-memory computing.

Memristive stateful logic allows complete in‐memory computing and is considered to be a next‐generation computing technology for low power edge applications. Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near‐memory error correction method for a typical bipolar‐type memristor stateful logic system is proposed. An error correction principles using a HfO2‐based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one‐bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.