A memristive crossbar array (MCA) is an ideal platform for emerging memory and neuromorphic hardware due to its high bitwise density capability. A charge trap memristor (CTM) is an attractive candidate for the memristor cell of the MCA, because the embodied rectifying characteristic frees it from the sneak current issue. Although the potential of the CTM devices has been suggested, their practical viability needs to be further proved. Here, a Pt/Ta 2 O 5 /Nb 2 O 5‐ x /Al 2 O 3‐ y /Ti CTM stack exhibiting high retention and array‐level uniformity is proposed, allowing a highly reliable selector‐less MCA. It shows high self‐rectifying and nonlinear current‐voltage characteristics below 1 µA of programming current with a continuous analog switching behavior. Also, its retention is longer than 10 5 s at 150 °C, suggesting the device is highly stable for non‐volatile analog applications. A plausible band diagram model is proposed based on the electronic spectroscopy results and conduction mechanism analysis. The self‐rectifying and nonlinear characteristics allow reducing the on‐chip training energy consumption by 71% for the MNIST dataset training task with an optimized programming scheme.
Memristive stateful logic enables energy‐ and cost‐efficient in‐memory computing, which is desirable for edge computing in the coming Internet of Things (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system‐level in‐memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1‐transistor−1‐memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look‐ahead adder. Then, an in‐memory computing layout that can perform all of the computing functions—data storing, transferring, and executing—inside the memory, addressing data traffic issues, is suggested. Finally, a software/hardware mixed stateful logic emulator that can virtually mimic array‐level in‐memory computing hardware based on cell‐level memristive characteristics is demonstrated.
A memristive stateful neural network allowing complete Boolean in-memory computing attracts high interest in future electronics. Various Boolean logic gates and functions demonstrated so far confirm their practical potential as an emerging computing device. However, spatio-temporal efficiency of the stateful logic is still too limited to replace conventional computing technologies. This study proposes a ternary-state memristor device (simply a ternary memristor) for application to ternary stateful logic. The ternary-state implementable memristor device is developed with bilayered tantalum oxide by precisely controlling the oxygen content in each oxide layer. The device can operate 157 ternary logic gates in one operational clock, which allows an experimental demonstration of a functionally complete three-valued Łukasiewicz logic system. An optimized logic cascading strategy with possible ternary gates is ≈20% more efficient than conventional binary stateful logic, suggesting it can be beneficial for higher performance in-memory computing.
Memristive neural networks perform vector matrix multiplication efficiently, which is used for the accelerator of neuromorphic computing. To train the memristor cells in a memristive neural network, the analog conductance state of the memristor should be programmed in parallel; otherwise, the resulting long training time can limit the size of the neural network. Herein, a novel parallel programming method using the self‐limited analog switching behavior of the memristor is proposed. A Pt/Ti:NbOx/NbOx/TiN charge trap memristor device for the programming demonstration is utilized, and a convolutional neural network is emulated to train the MNIST dataset, based on the device characteristics. In the simulation, the proposed programming method is able to reduce programming time to as low as 1/130, compared with the sequential programming method. The simulation suggests that the programming time required by the proposed method is not affected by array size, which makes it very promising in a high‐density neural network.
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