Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Abstract

To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

“…One recent modification of IMPLY logic is ORNOR [35], which enables threeinput logic operations, thus improving the overall computing latency compared to original IMPLY-based operations. We included in this comparison the work by Reuben et al in Reference [36], which presented an accelerated MAJ-based execution of binary addition, compared to previous work, such as Reference [18]. By observing Table 6, we conclude that, the smaller the area, the larger the number of total steps needed, especially for the IMPLY-based schemes, which require many sequential operations while occupying just two cross-points.…”

“…All in all, the proposed computing approach requires almost 50% less crosspoints, compared to schemes that perform parallel computations, while taking the least possible cycles. The only exception is the MAJ+NOT style [36], which clearly outperforms the rest in computing steps. However, this comes at the cost of larger area, since it requires more than 12× the number of memristors used by the proposed approach.…”

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles

“…5. The operational amplifier acts as a voltage regulator and is also able to deliver the required current to program eight 1T-1R cells simultaneously [5]. Writing binary data is straightforward in ReRAM technology -the cell is programmed to LRS (the filament is formed between the electrodes) by applying a positive voltage to the BL while SL is grounded.…”

“…Although there had been a plethora of works on in-memory arithmetic, it is evident that latency of such in-memory adders has not been carefully studied and optimized. As a result, they require hundreds of cycles to perform 32-bit addition in memory [5]. This exorbitant latency (O(n) for adding two nbit numbers) can be attributed to rippling of carry and weak logic primitives used (IMPLY/NOR).…”

“…To avoid rippling of carry, parallel-prefix adders were investigated. Parallel-prefix adders could reduce the latency of in-memory addition to 8•O(log(n)) and 4•O(log(n)) using OR/AND primitives [9] and MAJORITY/NOT [5], respectively.…”