The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-ƙ dielectrics. The high-ƙ dielectric material in the place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (DG) MOSFET has been proposed. The capacitance modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the results derived from previous research and tabulated. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF hybrid applications.