Speed enhancement and kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters

An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.

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Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

Kazeminia

Mahdavi²

2019

International Journal of Electronics

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Speed enhancement and kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters

Cited by 6 publications

References 3 publications

Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

Regenerative comparator with floating capacitor for energy‐harvesting applications

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

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